Senior IC Layout Design Engineer

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$156,480–$234,720 / yr
Posted
18 days ago
Freshness
Confirmed live today
Closes
Oct 8, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $196k
$138k $245k
below market most similar roles pay here above market

This role pays more than 55% of similar roles. Most pay $167,812–$216,562 — the blue band above. At the midpoint, this role pays about $196k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · Senior IC Layout Design Engineer

The Senior IC Layout design Engineer joins the SerDes Technology Group to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. This role involves the layout design of high-speed analog mixed-signal circuits, including block-level physical implementation, floor-planning, power distribution networks, and clock and signal routing. The engineer will participate in post-layout performance analysis, chip-level integration, and defining layout methodologies while supervising layout resources and driving productivity improvements like pcell development. Key technical requirements include experience with 7nm or lower process nodes, understanding of IR, EM, and RC delay, and proficiency in physical design verifications such as LVS, DRC, and ERC. Candidates should be familiar with high-speed SerDes blocks, PLLs, and tools like Cadence SKILL, Perl, Python, or Tcl.

What you'll do

  • Design high-speed SerDes analog mixed-signal circuits according to project specifications.
  • Execute block-level physical implementation including floor-planning, power distribution, and signal routing.
  • Perform post-layout circuit performance analysis and block/IP/chip level integration.
  • Define layout methodologies and flows to improve overall layout productivity.
  • Develop pcells and automation tools to drive layout productivity initiatives.
  • Supervise onsite and offsite layout resources while correcting quality issues.
  • Provide technical feedback to design teams and report on project progress.

What we're looking for

  • Bachelor degree in EE/CE or IC layout training Certificate with IC Layout working experience.
  • Experience in analog/mixed-signal layout design with a supervisory role.
  • Experience in layout design of high-speed SerDes blocks and PLLs in advanced Fin-FET process (preferred).
  • Experience in layout design in lower process nodes of 7nm or below (preferred).
  • Experience with Cadence SKILL and other programming languages like Perl, Python, or Tcl (preferred).
  • Experience with digital on top integration flow or digital SOC flow (preferred).
  • Strong understanding of analog and mixed-signal layout fundamentals, including IR, EM, and RC delay (preferred).
  • Strong understanding of high-speed critical signal routing, shielding, and physical design verifications (preferred).

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