The Mask Layout Designer joins the QCT WAN RFIC design group to perform physical design for RF and analog circuits. This role involves detailed custom layout tasks including floorplan, placement, routing, and verification for high frequency RF circuits. The designer is responsible for delivering final databases, debugging complex verification errors, mentoring junior designers, and managing project milestones. Key technical requirements include experience with chip, block, and device level layouts for components like LNAs, mixers, and VCOs. Candidates must utilize Cadence Virtuoso XL and Siemens Caliber DRC/ERC/LVS tools. Proficiency in automation scripting using SKILL, Python, and Perl is required to improve layout efficiency and data checks. The work focuses on solving high frequency RF circuit challenges through top down and bottom up chip design.
Perform physical design of RF and analog circuits including floorplan, placement, and routing.
Execute detailed custom layout and release final databases for high-frequency RF circuits.
Debug complex verification errors and ensure layout meets all design requirements.
Develop and maintain automation scripts using SKILL, Python, and Perl to improve layout efficiency.
Provide accurate schedules and plans to meet project milestones.
Mentor junior layout designers and lead teams to deliver high-quality layout results.
Manage chip design processes from top-down and bottom-up through tapeout.
What we're looking for
Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts.
Associate's degree in Computer Science, Mathematics, Electrical Engineering, or related field and 4+ years of experience designing custom layouts.
High School diploma or equivalent and 6+ years of experience designing custom layouts in a relevant domain.
Experience in RF high frequency circuit custom layout at chip, block, and device levels.
2+ years of experience using layout design and verification tools such as Cadence, LVS, or rmap.
Basic automation scripting skills in SKILL, Python, and/or Perl for layout and verification flows.
Proficiency in Cadence Virtuoso XL (preferred).
Experience with Siemens Caliber DRC/ERC/LVS verification and debugging tools (preferred).