Layout/Mask Designer

As a Layout/Mask Designer, you will join the hardware team to design complex custom layouts for digital circuits using deep SubMicron CMOS technologies. Your daily responsibilities include reviewing floorplans with circuit designers, negotiating layout tradeoffs, and utilizing advanced CAD tools to ensure robust physical design representation. You will perform EMIR simulations to ensure power delivery, interpret LVS, DRC, and ERC reports to resolve issues, and use automated P&R tools to accelerate execution. The role requires expertise in Cadence Virtuoso, standard cell planning, and hierarchical layout assembly while addressing challenges like RC delay, electromigration, and cross-capacitance. You will also design low noise, low power data-path or memory structures. This position focuses on achieving best-in-class PPA for critical designs within the domain of high-performance digital circuit integration and physical design verification.