This role pays more than
57%
of similar roles. Most pay
$169,875–$216,250
— the shaded band above.
At the midpoint, this role pays about
$192k
versus about
$193k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
1047 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 833 roles with salary data.
As a Senior Photonic Layout Design Engineer, you will join a multidisciplinary team of photonics, CMOS, packaging, and systems engineers to develop next-generation Silicon Photonics and SERDES products. You will take ownership of the physical design and verification of photonic integrated circuits, guiding them from proof-of-concept to manufacturing readiness. Your daily responsibilities include manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions like high-speed I/Os and ESD structures. You will manage floor planning, waveguide routing, mask data preparation, and rigorous post-layout verification including DRC, LVS, and density checks. To succeed, you must utilize Cadence Virtuoso, Calibre, Hercules, ICV, or Dracula while leveraging Python, SKILL, Perl, TCL, or C++ to develop AI-assisted design methods and automation scripts for complex high-density chip designs within advanced sub-micron CMOS and SiPh technologies.
Lead full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions.
Manage the entire tape-out process including floor planning, waveguide routing, and mask data preparation.
Execute rigorous post-layout verification including DRC, LVS, fill, and density across multiple design versions.
Identify and mitigate layout-dependent issues to ensure clean designs prior to manufacturing.
Design complex test structures, active/passive full loops, and certification vehicles for process window optimization.
Develop AI-assisted design methods and automation scripts to improve productivity and reduce development cycles.
Create custom Pcells and automated tools to customize DRC and LVS checking flows.
What we're looking for
BS, MS, or Ph.D. in Electrical Engineering, Physics, or a closely related field (or equivalent experience).
At least 12+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries.
Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies.
Proven expertise with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites like Calibre, Hercules, ICV, Dracula, or Primeyield.
Strong proficiency in programming and scripting languages including Python, SKILL, Perl, TCL, or C++ for layout automation and data processing.
Ability to optimize workflows using best-known methods and collaborate with integration and design rule teams to achieve high-yield manufacturing goals.