As a Senior Photonic Layout Design Engineer, you will join a dynamic team of experts in Silicon Photonics (SiPh) to lead the physical design and verification of advanced photonic integrated circuits (PICs), guiding them from concept to high-volume manufacturing. Your responsibilities include executing complex layout designs for waveguides, modulators, and mixed-signal functions, driving rigorous post-layout verification processes, and developing AI-assisted workflows to enhance productivity. You will need a deep understanding of semiconductor fabrication, proficiency in Cadence Virtuoso and Calibre verification suites, and strong scripting skills with Python or C++. This role requires at least 6 years of experience in full-chip layout design within the semiconductor industry, focusing on Silicon Photonic constraints and device physics.
Skills
Cadence_Virtuoso
Calibre
Python
TCL
Perl
SKILL
C++
AI
Automation
DOE
DRC
LVS
Silicon_Photonics
CMOS
Custom_Layout
SDL
ICV
Dracula
Primeyield
What you'll do
Lead complex layout designs for waveguides, modulators, photodetectors, and mixed-signal functions.
Drive full tape-out process including floor planning, waveguide routing, and mask data preparation.
Execute rigorous post-layout verification to ensure DRC/LVS cleanliness before tape-out.
Develop and own the layout of complex test structures and certification vehicles for optimization.
Implement AI-assisted design methods and custom Pcells to improve productivity and reduce cycle times.
What we're looking for
At least 6+ years of full-chip layout design experience in semiconductor or silicon photonics industries.
Deep understanding of analog circuit layout and Silicon Photonic constraints within advanced sub-micron CMOS technologies.
Proven expertise with Cadence Virtuoso and industry-standard verification suites like Calibre, ICV, Dracula, or Primeyield.
Strong proficiency in programming languages for layout automation and tape-out flows, including Python, SKILL, Perl, TCL, or C++.
Ability to develop AI-assisted design methods and custom Pcells to improve productivity and customize DRC/LVS checking flows.
Ownership of complex test structures and certification vehicles with large Design of Experiments (DOEs) for process optimization.
Market check
Salary context
This
$132,000–$207,000
range sits above
40%
of similar postings on FindRole.
Peer median band
$141,600–$218,500
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$154,525–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.*
* 240 is the maximum number of comparable postings sampled.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
801 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 797 roles with salary data.
Us, Ca, Santa Clara, US119 days ago
$168,000–$264,500
Spice
Python
Perl
Tcl
Make
RTL
Logic Synthesis
Verification
Auto Place and Route
STA
PnR
DRC
LVS
Power Gating
Multi-Vt
Post-Silicon Characterization
Custom Circuit Design
Semi-Custom Circuit Design
Altium Designer
Python
MATLAB
C
Xilinx FPGAs
Vivado IDE
USB 3.0
10Gb Ethernet
I2C
RS232
FCC
CE Mark
MIL-STD-461
DMM
Oscilloscope
Logic Analyzer
Spectrum Analyzer
Altium Designer
Python
C
MS Office
Google Suite
MIL-STD
DMM
Bench top supply
Oscilloscope
Logic analyzer
Spectrum analyzer
USB 3.0
10Gb Ethernet
RS232
Xilinx FPGAs
HDI routing