Digital Layout Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 66 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $207k

$138k most similar roles pay here $263k

This listing doesn't post a salary. Most similar roles pay $170,869–$243,600.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · Digital Layout Design Engineer

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As a Digital Layout Design Engineer within the Digital Design Engineering group, you will join the microprocessor group's custom layout team to develop state-of-the-art ASICs and digital macros using the latest technology nodes. You will be responsible for delivering PDV clean layouts by designing complex custom layouts for digital circuits in deep SubMicron CMOS technologies. Your daily work involves analyzing floorplans with circuit designers, running verification tools on megacells, and interpreting LVS, DRC, and ERC reports to resolve layout issues. You will utilize advanced CAD tools and mask design knowledge to ensure robust physical designs. Required skills include proficiency in floorplanning, standard cell planning, and hierarchical assembly while addressing RC delay, electromigration, and self-heating. Experience with MENTOR GRAPHICS or CADENCE tools is required, with optional expertise in CSH, PERL, SKILL scripting, and memory compiler development.

Skills

Digital Layout ASIC SubMicron CMOS Floorplanning Standard Cell Planning LVS DRC ERC CALIBRE Mentor Graphics Cadence CSH Perl SKILL Layout Automation Memory Compiler Development

What you'll do

Design complex custom layouts for digital circuits using deep SubMicron CMOS technologies.
Analyze floorplans and complex circuits in collaboration with circuit designers.
Execute a complete set of layout design verification tools on completed megacells.
Negotiate layout tradeoffs and manage project schedules with the circuit design team.
Interpret LVS, DRC, and ERC reports to identify and resolve layout issues efficiently.
Utilize advanced CAD tools and mask design knowledge to ensure robust physical designs.
Address technical challenges related to RC delay, electromigration, self-heating, and cross-capacitance.

What we're looking for

Bachelor's degree in a relevant field of study.
10 years of relevant experience.
Experience in custom layout design of deep SubMicron CMOS circuits (preferred).
Proficiency in floorplanning, standard cell planning, and hierarchical layout assembly (preferred).
Understanding of RC delay, electromigration, self-heating, and cross capacitance issues (preferred).
Ability to interpret CALIBRE DRC, ERC, and LVS reports (preferred).
Knowledge of MENTOR GRAPHICS or CADENCE layout tools (preferred).
Skills in CSH, PERL, SKILL scripting, layout automation, or memory compiler development (preferred).