CPU SRAM Design & Layout Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$147,900–$221,900 / yr
Posted
25 days ago
Freshness
Confirmed live today
Closes
Mar 8, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $207k
This role $185k
$134k most similar roles pay here $277k

This role pays less than 66% of similar roles. Most pay $176,600–$238,387 — the shaded band above. At the midpoint, this role pays about $185k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 564 open roles on FindRole.

Listed pay typically runs $152,800–$222,500 across 545 roles with salary data.

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At a glance

TL;DR · CPU SRAM Design & Layout Engineer

As a CPU SRAM Design & Layout Engineer on the High Performance CPU Team, you will manage the design, analysis, implementation, and physical realization of high-performance custom SRAMs and register files. You will own memory development from initial schematic capture and circuit design through layout implementation, verification, characterization, and model generation. The role involves collaborating with CAD and physical design teams to optimize for performance, power, area, and reliability. Key responsibilities include creating floorplans, performing LVS/DRC checks, and conducting timing and electrical characterization. You will utilize industry-standard tools including Cadence Virtuoso, Calibre, NanoTime, Ansys EMIR, ESP-CV, and Liberate. Technical expertise required includes FinFET and nanosheet process nodes, Monte Carlo analysis, static timing analysis, Verilog for logical models, and SKILL scripting to solve complex memory PPA challenges in advanced semiconductor technologies.

What you'll do

  • Design and develop custom SRAM and register file circuits optimized for performance, power, and area.
  • Create schematics and perform circuit-level design and optimization for memory components.
  • Develop memory floorplans and execute custom layout designs based on project requirements.
  • Perform physical verification including LVS, DRC, and ERC to ensure manufacturable layouts.
  • Execute functional verification, simulation, and margin analysis across various process, voltage, and temperature conditions.
  • Conduct timing, power, and electrical characterization of memory designs.
  • Generate and validate required memory deliverables, collateral models, and automation scripts.
  • Provide technical recommendations for memory architecture, layout strategy, and PPA optimization.

What we're looking for

  • Bachelor's degree in Electrical Engineering or related field with 5+ years of experience, Master's with 2+ years, or a PhD.
  • Experience designing custom SRAM circuits and register files.
  • Experience with custom memory layout design, implementation, and deep sub-micron layouts for memory and datapath.
  • Proficiency with Cadence Virtuoso and Calibre LVS/DRC verification flows.
  • Experience with circuit simulation, Monte Carlo analysis, and static timing analysis.
  • Knowledge of advanced semiconductor technologies including FinFET and nanosheet process nodes.
  • Knowledge of layout floorplanning, hierarchical assembly, and physical verification methodologies.
  • Strong understanding of high-performance and low-power circuit design techniques (preferred).

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