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Fabric Interconnect Design Verification Engineer | Microsoft Careers

Microsoft

US 3 days ago $102,100–$202,200
Actively hiring Posted this week Verified listing Below market
UVM System Verilog Python Coherent Hub Interface (CHI) cache coherency architectures Universal Verification Methodology (UVM) System Verilog Test Bench (SVTB) generative AI C++ Perl Tcl
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Data Cache & Coherent Interconnect Architect/Engineer (Multiple Levels)

Qualcomm

Austin, TX 4 days ago $154,000–$252,800
Actively hiring Posted this week Competitive pay
C/C++ Verilog SystemVerilog CHI ACE Cache coherence protocols Data caches Coherent interconnects Processor architecture Micro-architecture IP development Performance analysis SoC integration System-level performance modeling
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Senior Design Engineer, Coherent High Speed Interconnect

Nvidia

Santa Clara, CA 22 days ago $168,000–$264,500
Actively hiring Above market
PCIe CXL AXI CHI Verilog SystemVerilog RTL design performance analysis power optimization Data link layer Physical layer Memory (DDR, LPDDR) SerDes Python CI/CD
Hybrid
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SoC Architect, Coherent Interconnect

Samsung Electronics

Remote (3655 N 1St St, San Jose, Ca, Usa, US) 51 days ago $180,200–$297,200
Actively hiring Above market
C C++ Python Verilog VHDL AXI ACE CHI PCIe USB Linux Android Arm Architecture Cache Coherence Protocols MESI MOESI Network-on-Chip System-Level Design Simulation Tools Modeling Benchmarking
Remote
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