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UVM Formal Verification Python PCIe CXL AMBA CHI Fabric Interconnects Assertions Coverage Simulation Data Analysis Automation AI-driven solutions +9 more Show less

RTL Design ASIC Design Microarchitecture CPU GPU NoC Cache Coherency Physical Design Silicon +5 more Show less

SystemVerilog UVM Constrained-Random Verification Coverage-Driven Verification Python Perl Shell ASIC Verification RTL CHI AXI FPGA Emulation Coherent Interconnects +9 more Show less

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects Coherency Simulation Test Bench IP Verification Post-processing +9 more Show less

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects SOC Simulation Verification Environments Post-processing +8 more Show less

RTL NoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration SoC Front-end Synthesis +10 more Show less

RTL NoC SoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration Scripting Front-end Synthesis +11 more Show less

Semiconductor Fabrication Quantum Transduction Single-Photon Detection Quantum Memory Cryogenic Characterization Heterogeneous Integration Materials Engineering Device Design Process Engineering +4 more Show less

SerDes PAM4 Signal Integrity Power Integrity PCB Design Advanced Packaging ADS HFSS CST HSPICE MATLAB Python Cadence Sigrity PowerSI Clarity SystemVerilog Verilog-A IBIS-AMI Ethernet PCIe NVLink UCIe FEC +18 more Show less

RTL Design Verilog SystemVerilog ASIC Design Flow STA DFT ECO AMBA5 CHI AMBA4 ACE AXI Coherent Interconnect LLC Python Perl Computer Architecture Memory Subsystem Architecture +11 more Show less

MATLAB Python SystemC Verilog RTL SerDes UCIe Monte Carlo Signal Integrity Communication Theory Algorithm Verification Silicon Correlation Hardware Architecture Analog Non-idealities +9 more Show less

System Verilog UVM RTL Design Python Perl Formal Verification AMBA AXI ACE CHI Microarchitecture Cache Coherence Data Structures Algorithms Object-Oriented Programming +10 more Show less

Electrical Engineering Ethernet EtherCAT CAN RS-232/485 USB Python Matlab EMI/EMC Signal Integrity SECS/GEM SolidWorks Electrical EPLAN Zuken Oscilloscopes Protocol Analyzers DOE Data Analysis +13 more Show less

Verilog System Verilog RTL Design C C++ Python Perl x86 ARM Digital Design DFT MMU High-Speed Design +8 more Show less

SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols +7 more Show less

SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols +7 more Show less

Signal Integrity (SI) Power Delivery Network (PDN) ASIC SerDes Silicon Photonics Co-Packaged Optics (CPO) Co-Packaged Copper (CPC) On-Board Optics (OBO) Firmware FEC Lab Bring-up Validation Debug PCI-SIG IEEE +10 more Show less

RTL NoC SoC Synthesis STA CDC Lint MESI MOESI Directory-based coherence Cache Coherency Memory Hierarchy Crossbars Arbitration Scripting +10 more Show less

RTL NoC ASIC Design Synthesis STA CDC Lint Cache Coherency MESI MOESI Memory Hierarchy Crossbars Arbitration Front-end Synthesis +9 more Show less

RTL ASIC Design NoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Memory Hierarchy Crossbars Arbitration SoC Scripting +10 more Show less