Senior Leader, Signal and Power Integrity/Systems Architecture (High-Speed Interconnects)

What you'll do

• Define end-to-end architecture for 224G and 448G PAM4 electrical interconnect systems.
• Lead system-level Signal Integrity and Power Integrity strategies including channel budgeting and COM analysis.
• Drive architecture, modeling, and optimization for high-speed link technologies and equalization techniques.
• Develop and productize advanced electrical connectivity solutions using advanced packaging and PCB technologies.
• Provide technical leadership for future interconnect roadmaps and scalable AI infrastructure innovations.
• Perform simulation-to-silicon correlation for PDN design, jitter, crosstalk, and insertion loss.

What we're looking for

• MS or PhD in Electrical Engineering, Computer Engineering, Physics, or a related discipline.
• Bachelor's degree in Chemical, Electrical, or Mechanical Engineering with 10+ years of System/Package Design/Technology Engineering experience.
• Master's degree in Chemical, Electrical, or Mechanical Engineering with 9+ years of System/Package Design/Technology Engineering experience.
• PhD in Chemical, Electrical, or Mechanical Engineering with 8+ years of System/Package Design/Technology Engineering experience.
• 15+ years of experience developing high-speed communication, networking, or datacenter infrastructure products.
• Demonstrated success productizing 112G and/or 224G PAM4 electrical communication systems.
• Deep expertise in high-speed SerDes, PAM4, SI/PI, advanced packaging, PCB design, and power delivery networks.
• Hands-on experience with ADS, HFSS, CST, HSPICE, MATLAB, Python, Cadence Sigrity, PowerSI, Clarity, SystemVerilog, Verilog-A, and IBIS-AMI modeling.