Principal Micro-architect, Coherent Interconnect

Samsung Electronics

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CAAustin, TX
Salary
$221,700–$364,800 / yr
Employment
Full-time
Posted
15 days ago
Freshness
Confirmed live today
Closes
Mar 31, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $230k
This role $293k
$156k $387k
below market most similar roles pay here above market

This role pays more than 88% of similar roles. Most pay $195,556–$265,243 — the blue band above. At the midpoint, this role pays about $293k versus about $230k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 94 open roles on FindRole.

Listed pay typically runs $106,000–$174,500 across 85 roles with salary data.

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At a glance

TL;DR · Principal Micro-architect, Coherent Interconnect

Role Posting Log in to save

The Principal Micro-architect joins the System IP team to lead the microarchitecture development of custom coherent interconnect IP and last-level cache blocks for next-generation designs. This role involves driving RTL design, performance and power optimization, logic debug, and timing closure while collaborating with system architects to define specifications. The successful candidate will own the delivery of high-quality RTL implementations that meet PPA goals and provide technical mentorship to junior engineers. Required expertise includes computer architecture, memory subsystem architecture, and coherent cache design. Key technologies include Verilog, SystemVerilog, and scripting languages like Perl or Python. Candidates must demonstrate proficiency with on-chip network topologies such as mesh, ring, and crossbar interconnects, alongside protocols like Arm AMBA5 CHI, AMBA4 ACE, and AXI.

Skills

RTL Design Verilog SystemVerilog ASIC Design Flow STA DFT ECO AMBA5 CHI AMBA4 ACE AXI Coherent Interconnect LLC Python Perl Computer Architecture Memory Subsystem Architecture

What you'll do

  • Lead the microarchitecture development of custom coherent interconnect IP and last-level cache blocks.
  • Drive coherent interconnect RTL design including performance and power optimization, logic debug, and timing closure.
  • Define microarchitecture specifications from early architectural exploration through detailed research and refinement.
  • Develop high-quality RTL implementations that meet specific performance, power, and area goals.
  • Partner with verification teams to ensure functional correctness and robust validation of the design.
  • Collaborate with physical design and CAD teams to resolve implementation, timing, and integration challenges.
  • Provide technical leadership and mentorship to junior engineers across the team.

What we're looking for

  • Must have a Bachelor’s degree with 15+ years of experience, a Master’s with 13+ years, or a PhD with 11+ years of experience.
  • Must have a strong background driving RTL design of coherent interconnect and LLC sub-blocks for high-performance digital designs.
  • Must have demonstrated experience spanning architecture definition through RTL implementation.
  • Must have familiarity with on-chip network topologies and working knowledge of Arm AMBA5 CHI, AMBA4 ACE, AXI, and related protocols.
  • Must have deep expertise in Verilog/SystemVerilog and a solid understanding of the complete ASIC design flow.
  • Must have a strong understanding of memory subsystem architecture, coherent cache design, and directory-based snoop filter protocols.
  • Must have proven experience leading technical initiatives, mentoring engineers, and collaborating across geographically distributed teams.
  • Export Control This role may require access to information subject to U.S. export control laws.

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