Technical Fellow - High-Speed Interconnect & Optics

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$284,800–$427,200 / yr
Posted
10 days ago
Freshness
Confirmed live yesterday
Closes
Sep 23, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k
This role $356k
$132k most similar roles pay here $459k

This role pays more than 99% of similar roles. Most pay $172,000–$233,050 — the shaded band above. At the midpoint, this role pays about $356k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 498 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 498 roles with salary data.

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At a glance

TL;DR · Technical Fellow - High-Speed Interconnect & Optics

Technical Fellow - High-Speed Interconnect & Optics serves as a senior technical leader defining and advancing system-level interconnect architecture for next-generation AI, HPC, and data center platforms. The role involves driving innovation across electrical and optical technologies including ASICs, advanced packaging, boards, and optics to enable scalable system architectures. Key responsibilities include providing authority in high-speed signal integrity and power delivery networks at 112G and 224G rates, leading optical system integration involving silicon photonics and laser integration, and guiding SerDes and ASIC co-optimization. The candidate will perform hands-on technical leadership during lab bring-up and debug while representing the company in industry standards bodies like OIF, IEEE, and PCI-SIG. Required expertise includes pluggable optics, CPO, CPC, OBO, and advanced packaging to solve complex interconnect challenges for high-density systems.

What you'll do

  • Define and advance system-level interconnect architecture for next-generation AI, HPC, and data center platforms.
  • Provide technical leadership in high-speed signal integrity (SI) and power delivery network (PDN) design across ASICs and boards.
  • Drive end-to-end optical system integration including silicon photonics, advanced packaging, and thermal management.
  • Coordinate SerDes architecture and ASIC co-optimization to align with real-world channel behavior and packaging constraints.
  • Serve as a hands-on technical authority for lab bring-up, characterization, and complex cross-layer system debugging.
  • Represent the company in industry standards bodies to influence next-generation specifications and ecosystem alignment.
  • Mentor senior engineers and establish architectural frameworks to improve technical excellence across business units.
  • Advise senior leadership on technical trade-offs, vendor strategies, and product go/no-go decisions.

What we're looking for

  • Master's degree in Computer Science, Electrical Engineering, Photonics, or a related technical field.
  • Expertise in high-speed signal integrity and power delivery network (SI/PI, PDN) design for 112G, 224G, and beyond (preferred).
  • Experience with optical interconnect technologies including pluggable optics, CPO, CPC, and OBO (preferred).
  • Experience in optical packaging, silicon photonics, laser integration, and thermal/power management (preferred).
  • Hands-on experience with system bring-up, validation, and debug across ASICs, packages, boards, and optical subsystems (preferred).
  • Strong understanding of SerDes architecture, equalization, FEC, and system-level channel modeling (preferred).
  • Recognized industry or academic thought leader with publications and patents (preferred).

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