Senior Verification Engineer, High Speed Coherent Interconnect Hub

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
7 days ago
Freshness
Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $195k
This role $177k
$125k $241k
below market most similar roles pay here above market

This role pays less than 57% of similar roles. Most pay $173,781–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $195k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Verification Engineer, High Speed Coherent Interconnect Hub

Senior Verification Engineer – High Speed Coherent Interconnect Hub joins the Tegra SoC IP Verification team to verify complex High Speed Coherent Interconnect Hub IP. The role involves defining verification strategies, developing robust verification environments, and driving functional and performance verification to ensure high-quality design signoff. Key responsibilities include developing testbenches, BFMs, checkers, monitors, scoreboards, assertions, and constrained-random stimulus. The engineer will define test plans for coherency protocols, ordering, error handling, and performance requirements like bandwidth, latency, and QoS. Required skills include SystemVerilog, UVM, constrained-random verification, and coverage-driven methodologies. Candidates should possess experience with ASIC verification, debugging tools, and scripting in Python, Perl, or Shell. The work focuses on verifying high-speed coherent interconnects, NoCs, and cache coherency for multi-chip computing platforms.

What you'll do

  • Develop and maintain verification infrastructure including testbenches, BFMs, checkers, monitors, scoreboards, and assertions.
  • Define and complete verification test plans for coherency protocols, ordering, error handling, and performance.
  • Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces.
  • Develop performance test plans to validate bandwidth, latency, and QoS requirements.
  • Drive functional and code coverage closure to provide verification signoff.
  • Debug complex RTL and verification issues in coordination with architecture and design teams.
  • Support system validation and silicon bring-up with FPGA, emulation, software, and post-silicon teams.

What we're looking for

  • BS / MS or equivalent experience.
  • 3+ years of ASIC verification experience with complex IPs or SoC subsystems.
  • Strong background in SystemVerilog, UVM, constrained-random verification, and coverage-driven verification methodologies.
  • Experience developing verification environments, checkers, assertions, and functional coverage.
  • Strong debugging and problem-solving skills with experience using industry-standard simulation and debug tools.
  • Experience verifying high-speed coherent interconnects, NoCs, or other complex SoC infrastructure IP (preferred).
  • Knowledge of coherent interconnect protocols and technologies such as CHI and AXI (preferred).
  • Strong scripting skills in Python, Perl, or Shell, along with excellent communication and collaboration skills (preferred).

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