Principal Die-to-Die Interconnect Modeling Architect

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CAFort Collins, CO
Salary
$167,500–$268,000 / yr
Employment
Full-time
Posted
19 days ago
Freshness
Confirmed live today
Closes
Apr 6, 2027

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Competitive pay

How this pay compares to similar roles

Similar $218k
This role $218k
$154k $291k
below market most similar roles pay here above market

This role pays more than 52% of similar roles. Most pay $181,825–$254,750 — the blue band above. At the midpoint, this role pays about $218k versus about $218k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Principal Die-to-Die Interconnect Modeling Architect

The Principal Die-to-Die Interconnect Modeling Architect leads a technical team in building and evolving a foundational modeling platform for die-to-die PHY designs. The architect develops comprehensive behavioral and architectural models to predict link behavior, including BER, latency, throughput, and power consumption. Key responsibilities involve performing tradeoff analyses on signaling schemes, modeling transmitter and receiver interactions, and driving algorithm verification of Verilog implementations. The role requires utilizing MATLAB, Python, and SystemC to perform Monte Carlo evaluations and architectural verification with silicon correlation. The architect must apply communication theory to address equalization, timing recovery, and adaptive signal processing. This position solves complex technical problems in high-speed SerDes and short-reach die-to-die communication systems, ensuring robust operation across manufacturing conditions and various process, voltage, and temperature variations.

What you'll do

  • Develop comprehensive behavioral and architectural models to predict link behavior using MATLAB, Python, or SystemC.
  • Model transmitter, receiver, package, channel, clocking, and equalization interactions to predict BER, latency, and power consumption.
  • Perform architectural sensitivity analyses across process, voltage, temperature, aging, and various channel impairments.
  • Analyze equalization, timing recovery, and adaptive signal processing algorithms for numerical stability and hardware efficiency.
  • Define architectural verification strategies to ensure system requirements are traceable from concept through production silicon.
  • Drive correlation between behavioral models, RTL simulation, laboratory characterization, and production silicon measurements.
  • Lead architecture reviews and critical technical decision-making across multidisciplinary engineering organizations.
  • Mentor engineers in communication systems, modeling techniques, and architecture development.

What we're looking for

  • MS in Electrical Engineering or Computer Engineering with 15 or more years of related experience.
  • PhD in Electrical Engineering or Computer Engineering with 12 or more years of related experience.
  • Deep understanding of communication theory, equalization, and adaptive algorithms.
  • Experience in high-speed SerDes or D2D communication systems architecture.
  • Extensive experience developing behavioral and architectural models using MATLAB, Python, SystemC, or equivalent tools.
  • Experience with architecture model to RTL to verification.
  • Experience leading architectural verification, silicon correlation, and performance validation across multidisciplinary engineering teams.
  • Demonstrated expertise in D2D, UCIe, or other short-reach die-to-die communication (preferred).
  • Expertise in advanced packaging including silicon interposers, EMIB, hybrid bonding, and 3D integration (preferred).
  • Management experience (preferred).

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