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Python C/C++ SystemVerilog Terraform Docker CI/CD Prometheus Grafana Palladium Mentor Veloce Protium HAPS RISC-V x86 ARMv8 Linux RTOS Xen KVM +14 more Show less

SystemVerilog UVM Python Perl C++ ASIC Verification Emulation FormalVerification Docker CI/CD +6 more Show less

SystemVerilog UVM Python Perl Emulation FormalVerification SiliconBring-up Post-siliconDebug Scripting DataCenterTechnologies AINetworking ASICVerificationMethodologies +7 more Show less

SystemVerilog Python Perl Tcl Make CMake Shell FPGA SoC RTL AXI PCIe DDR Ethernet Synopsys_HAPS Synopsys_Protium Synopsys_Palladium CI/CD +13 more Show less

FPGA Verilog SystemVerilog Synopsys ProtoCompiler Xilinx Vivado Synopsys ZeBu Siemens Veloce Perl Shell Tcl Python C C++ DPI PLI SystemC PCIe CXL NVLink USB CHI LPDDR5 LPDDR6 DDR5 DDR6 USB4 USB3 +22 more Show less

C C++ Python Shell OpenGL OpenGL ES Vulkan Linux Android Verilog UVM Lauterbach RTL Logic Analyzers Scopes +10 more Show less

Verilog SystemVerilog C C++ Python Ruby Git Subversion Unix/Linux ARM Multiprocessor coherency Mmu Cache architectures Compilers Assembler Device drivers +11 more Show less

C/C++ Python Perl Ruby Debugging Protocol_Analyzers Oscilloscopes System_Architecture Technical_Debug Validation_Strategy +5 more Show less

Verilog SystemVerilog Python TCL C FPGA Xilinx Intel JTAG Veloce Palladium +6 more Show less