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Palladium Zebu Python Perl SystemVerilog Verilog Verdi SimVision Makefile Mixed-Signal SoC Emulation Waveform Debug RTL Design +8 more Show less

Palladium Pre-Silicon Emulation Bluetooth UWB Python C/C++ MATLAB Verilog VHDL RTL DSP PHY MAC CI/CD FPGA High-Level Synthesis Fixed-Point Design Register Maps SoC Architecture +14 more Show less

Verilog SystemVerilog Python TCL C FPGA Veloce Palladium JTAG ASIC Design Emulation Synthesis Place and Route Timing Closure SoC Architecture Kernel Debuggers Bus Protocols DDR NoC +14 more Show less

Verilog SystemVerilog Python TCL C FPGA Veloce Palladium JTAG ASIC Design SoC Architecture Timing Closure Synthesis Place and Route Kernel Debuggers Bus Protocols DDR NoC +13 more Show less

FPGA Prototyping Hardware Emulation Verilog SystemVerilog C/C++ Synopsys ZeBu Siemens Veloce Synopsys ProtoCompiler Xilinx Vivado Synplify Premier SystemC PCIe CXL NVLINK DPI PLI Python Perl Tcl Shell VCS Verdi GDB LPDDR5 DDR5 USB4 Logic Analyzers Oscilloscopes +23 more Show less

Verilog SystemVerilog Python C/C++ Tcl Emulation Zebu Palladium Pre-silicon Verification ASIC Ethernet PCIe IXIA Spirent Coverage-driven Verification DPI Scripting +12 more Show less

ASIC Design SoC Architecture RTL Design Verilog SystemVerilog FPGA Design Emulation Hardware Validation Hardware Debug C/C++ Python Tcl Perl Linux Embedded Linux CI/CD JTAG Git JIRA PCIe AXI Ethernet I2C Palladium Veloce MBIST ATPG +22 more Show less

SystemVerilog Verilog UVM Palladium Veloce Zebu FPGA Xilinx Altera Python Perl TCL C/C++ DPI RTL SystemVerilog Assertions Low Power Testing Emulation Design Verification +13 more Show less

GPU Architecture Pre-silicon Validation C/C++ Python Perl Ruby Synthesizable Code DPI Transactors 3D Graphics Pipeline Hardware Acceleration Simulation +7 more Show less

SystemVerilog Verilog C++ C UVM VHDL Python Perl TCL Makefile Palladium Veloce Zebu PCIe USB Power Estimation DPI Transactors +12 more Show less

SystemVerilog Verilog UVM Palladium Veloce Zebu Python Perl TCL C/C++ DPI FPGA Xilinx Altera RTL Design Verification SystemVerilog Assertions UVM Acceleration +12 more Show less

SystemVerilog Verilog UVM Palladium Veloce Zebu Python Perl TCL C/C++ DPI FPGA Xilinx Altera RTL Design Verification SystemVerilog Assertions Test FW +12 more Show less

SystemVerilog Verilog UVM Palladium Veloce Zebu FPGA Xilinx Altera Python Perl TCL C/C++ DPI RTL Design Verification SystemVerilog Assertions Low Power Testing +12 more Show less

SystemVerilog C++ C Python Perl Verilog RISCV Palladium Zebu Veloce FPGA Linux DPI Firmware +9 more Show less

Verilog System Verilog UVM FPGA Palladium Zebu Veloce C C++ Python Tcl Perl RTL Simulation Design Verification Synthesis Place and Route Timing Analysis Post-Silicon Debug +13 more Show less

System Verilog Verilog C++ C Python UVM FPGA Emulation x86 ARM Linux Windows Perl Makefile Shell Assembly RTL UEFI +13 more Show less

ZeBu Veloce Palladium ASIC RTL C/C++ Python Tcl Shell Hardware-Software Co-Verification Ethernet PCIe RDMA RoCE DMA Firmware Packet Processing Traffic Management QoS +14 more Show less

ASIC Emulation Cadence Palladium Mentor Veloce SystemVerilog Verilog VHDL C++ Python Tcl Perl Bare Metal ARM AMBA AXI4 UVM CI/CD Hardware Description Languages Embedded Firmware +12 more Show less

Cadence Palladium Synopsys ZeBu RTL SoC ARM Python Tcl Perl Shell AXI AHB APB Git Perforce CI/CD Waveform Analysis Signal Probing Assertion-based Debug Transactors +14 more Show less

C/C++ TCL Python System Verilog UVM OpenStack Docker Open vSwitch Palladium Veloce Zebu gdb RTL PCIe I2C Ethernet +11 more Show less