Emulation Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$184,700–$324,800 / yr
Posted
17 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 98% of similar roles. Most pay $168,425–$219,500 — the shaded band above. At the midpoint, this role pays about $255k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Emulation Verification Engineer

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As an Emulation Verification Engineer, you will join the design verification team focused on creating, deploying, and supporting sophisticated emulation environments for large SoCs. You will collaborate with Architecture, Design, Silicon Validation, Power, and Software teams to bring up systems on the Palladium platform while completing detailed test plans. Your daily responsibilities include developing synthesizable monitors, checkers, and stimulus, performing low power testing, and creating code to support emulation activities. The role requires proficiency in Verilog, SystemVerilog, UVM, C/C++ DPI, and scripting languages like Perl, Python, or TCL. You will also build random stimulus infrastructure by reusing existing UVM simulation constraints. This position addresses the technical challenge of verifying complex chip designs through advanced emulation flows involving tools such as Palladium, Veloce, Zebu, or FPGA platforms like Xilinx and Altera.

Skills

Palladium Veloce Zebu Xilinx Altera SystemVerilog Verilog UVM C++ Python Perl TCL FPGA RTL DPI Emulation Low Power Testing

What you'll do

  • Port large SoC designs onto the Palladium emulation platform.
  • Develop and apply synthesizable monitors, checkers, and stimulus for emulation environments.
  • Create and execute detailed test plans for complex SoCs.
  • Perform low power testing specifically on the emulation platform.
  • Write Verilog, SystemVerilog, and UVM code to support design and verification activities.
  • Build random stimulus infrastructure by reusing existing UVM simulation constraints.
  • Debug firmware and develop scripts using Perl, Python, or TCL.

What we're looking for

  • Minimum of BS degree and 10 years of relevant industry experience.
  • Understanding of the tool flow from RTL to Emulation (preferred).
  • Good understanding of any Standard Emulator or FPGA flow (preferred).
  • Proven design verification skills (preferred).
  • Experience writing synthesizable SystemVerilog/Verilog code and SystemVerilog assertions (preferred).
  • Experience with SystemVerilog verification environments including C/C++ DPI and UVM (preferred).
  • Experience writing and debugging test firmware (preferred).
  • Experience in any scripting language such as Perl, Python, or TCL (preferred).

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