Silicon Validation/Emulation Design Engineer

What you'll do

• Build and maintain Palladium emulation environments including compile flows, netlist preparation, and memory modeling.
• Perform system-level debug and root cause analysis of complex hardware issues on emulation platforms.
• Conduct IP-level debug and validation to isolate and resolve design issues with IP owners.
• Develop automation scripts and tools to improve build efficiency and platform utilization.
• Optimize emulation model performance through compile tuning, partitioning strategies, and configuration.
• Create reusable debug methodologies and documentation to accelerate issue resolution.
• Support pre-silicon hardware validation and integration for Wireless SoCs and ARM-based subsystems.

What we're looking for

• Bachelor of Science degree and at least 10 years of relevant industry experience.
• Experience with Cadence Palladium or equivalent platforms like Synopsys ZeBu (preferred).
• Proficiency in system-level and IP-level debug on emulation platforms (preferred).
• Experience with emulation compile flows, including synthesis, memory compilation, and clock modeling (preferred).
• Proficiency in debug tools such as waveform analysis, signal probing, and assertion-based debug (preferred).
• Understanding of RTL design, SoC architectures, ARM-based subsystems, and standard bus protocols like AXI, AHB, and APB (preferred).
• Experience developing automation scripts using Python, Tcl, Perl, or Shell (preferred).
• Experience with Wireless SoC applications such as Wi-Fi, Bluetooth, or cellular (preferred).