GPU Validation and Emulation Engineer, Senior

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $141,300–$211,900 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $206k

This role $177k

$128k $265k

below market most similar roles pay here above market

This role pays less than 82% of similar roles. Most pay $177,250–$235,750 — the blue band above. At the midpoint, this role pays about $177k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · GPU Validation and Emulation Engineer, Senior

Role Posting Log in to save

The GPU Validation and Emulation Engineer, Senior joins the GPU ASICS Engineering team to architect, design, and optimize the performance and power of GPU cores. This role involves synthesizing Verilog RTL to create models for emulators like Veloce, Palladium, and Zebu, as well as FPGA platforms. Key responsibilities include hardware emulator implementation, design partitioning, synthesis, place and route, and timing analysis. The engineer will drive debug failures, work on third-party IP integration, and support chip bring up and post-silicon debug. Required technical skills include Verilog, System Verilog, C, C++, and scripting in Python, Tcl, or Perl. The position focuses on solving hardware design verification problems, including system-level RTL simulation, functional and timing model debugging, and improving the area and performance of synthesized FPGA RTL.

Skills

Verilog System Verilog UVM FPGA Palladium Zebu Veloce C C++ Python Tcl Perl RTL Simulation Design Verification Synthesis Place and Route Timing Analysis Post-Silicon Debug

What you'll do

Synthesize Verilog RTL and create models for emulators like Veloce, Palladium, Zebu, and FPGA platforms.
Develop hardware emulator implementations focusing on design partitioning, synthesis, place and route, and timing analysis.
Drive debug failures on emulators using the latest technologies and work with designers on testplans.
Work with tool vendors to improve the area and performance of synthesized FPGA RTL.
Perform third-party IP integration and system-level debugging.
Conduct system-level RTL simulation and design verification.
Support chip bring-up and post-silicon debug activities.
Debug functional and timing models to ensure design accuracy.

What we're looking for

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of relevant work experience.
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 1+ year of relevant work experience.
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.
Verilog and System Verilog experience.
Programming skills in C and C++.
Scripting in Python, Tcl, or Perl.
Design Verification knowledge using UVM/System Verilog (preferred).
Knowledge of GPU/CPU/DDR/Bus (preferred).

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