Senior GPU Validation and Emulation Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$133,600–$200,400 / yr
Posted
59 days ago
Freshness
Confirmed live yesterday
Closes
Jan 10, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $206k
This role $167k
$121k most similar roles pay here $254k

This role pays less than 83% of similar roles. Most pay $177,250–$235,750 — the shaded band above. At the midpoint, this role pays about $167k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Senior GPU Validation and Emulation Engineer

Role Posting Log in to save

The GPU Validation and Emulation Engineer, Senior joins the GPU ASICS Engineering team to architect, design, implement, verify, and optimize the performance and power of GPU cores. This role involves synthesizing Verilog RTL, creating models, and compiling them for emulators like Veloce, Palladium, or Zebu, as well as FPGA platforms. The engineer will manage hardware emulator implementation, focusing on design partitioning, synthesis, place and route, timing analysis, and run-time performance. Key responsibilities include driving debug failures, integrating third-party IP, performing system-level RTL simulation, and supporting chip bring-up and post-silicon debug. Required technical skills include Verilog, SystemVerilog, C, C++, and scripting in Python, Tcl, or Perl. The role addresses critical hardware challenges involving GPU, CPU, DDR, and Bus architectures while utilizing Xilinx tools and advanced emulation methodologies like in-circuit emulation and simulation acceleration.

Skills

Verilog System Verilog UVM FPGA Palladium ZeBu Veloce Xilinx Altera C C++ Python Tcl Perl RTL Synthesis Post-Silicon Debug Simulation Acceleration

What you'll do

  • Synthesize Verilog RTL and create models for emulators such as Veloce, Palladium, Zebu, or FPGA platforms.
  • Develop hardware emulator implementations focusing on design partitioning, synthesis, place and route, and timing analysis.
  • Drive debug failures on emulators using the latest technologies in coordination with designers and software teams.
  • Collaborate with tool vendors to improve the area and performance of synthesized FPGA RTL.
  • Integrate third-party IP and perform system-level debugging.
  • Conduct system-level RTL simulation and design verification.
  • Support chip bring-up and post-silicon debug activities.
  • Debug functional and timing models for GPU cores.

What we're looking for

  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field with 2+ years of experience.
  • Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field with 1+ year of experience.
  • PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
  • Experience in hardware emulation, simulation acceleration, and FPGA platforms such as Xilinx or Altera.
  • Proficiency in Verilog and SystemVerilog for RTL synthesis and design verification.
  • Experience with hardware emulator platforms like Palladium, ZeBu, or Veloce.
  • Programming skills in C and C++ along with scripting in Python, Tcl, or Perl.
  • Knowledge of UVM, system-level debugging, and GPU/CPU/DDR architectures.

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