Emulation Verification Engineer

The Emulation Verification Engineer joins the design verification team to focus on creating, deploying, and supporting sophisticated emulation environments for large SoCs. Working at the center of a chip design effort, you will collaborate with Architecture, Design, Silicon Validation, Power, and Software teams to bring up systems on an emulation platform. Your daily responsibilities include porting designs onto the Palladium platform, completing detailed test plans, performing low power testing, and developing synthesizable monitors and checkers. You will build random stimulus infrastructure by reusing UVM simulation constraints and develop code for design and verification activities. Required skills include Verilog, SystemVerilog, UVM, C/C++ DPI, and scripting in Perl, Python, or TCL. The role addresses the technical challenge of verifying complex hardware designs using standard emulators like Palladium, Veloce, or Zebu to ensure functional product quality.