Emulation Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$184,700–$324,800 / yr
Posted
17 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 98% of similar roles. Most pay $168,425–$219,500 — the shaded band above. At the midpoint, this role pays about $255k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Emulation Verification Engineer

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The Emulation Verification Engineer joins the design verification team to focus on creating, deploying, and supporting sophisticated emulation environments for large SoCs. Working at the center of a chip design effort, you will collaborate with Architecture, Design, Silicon Validation, Power, and Software teams to bring up systems on an emulation platform. Daily responsibilities include porting designs onto the Palladium platform, completing detailed test plans, performing low power testing, and developing synthesizable monitors and checkers. You will develop code for design and verification using Verilog, SystemVerilog, UVM, and C/C++ DPI, while building random stimulus infrastructure from existing constraints. Required skills include experience with Perl, Python, or TCL scripting, as well as familiarity with standard emulators like Palladium, Veloce, or Zebu, and FPGA flows involving Xilinx or Altera hardware.

Skills

Palladium Veloce Zebu Xilinx Altera SystemVerilog Verilog UVM C++ DPI Python Perl TCL RTL FPGA Emulation Assertion

What you'll do

  • Port large SoC designs onto the Palladium emulation platform.
  • Develop and apply synthesizable monitors, checkers, and stimulus for the emulation platform.
  • Create and execute detailed emulation test plans in coordination with multi-functional teams.
  • Perform low power testing on the emulation platform.
  • Write Verilog, SystemVerilog, and UVM code to support design and verification activities.
  • Develop random stimulus infrastructure by reusing existing UVM simulation constraints.
  • Debug test firmware and develop scripts using Perl, Python, or TCL.

What we're looking for

  • Minimum of BS degree and 10 years of relevant industry experience.
  • Experience writing synthesizable SystemVerilog/Verilog code and SystemVerilog assertions (preferred).
  • Experience with SystemVerilog verification environments including C/C++ DPI and UVM (preferred).
  • Understanding of the tool flow from RTL to Emulation (preferred).
  • Good understanding of any Standard Emulator or FPGA flow (preferred).
  • Experience writing and debugging test firmware (preferred).
  • Experience in any scripting language such as Perl, Python, or TCL (preferred).
  • Experience in UVM Acceleration (preferred).

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