Emulation Verification Engineer

The Emulation Verification Engineer joins the design verification team to focus on creating, deploying, and supporting sophisticated emulation environments for large SoCs. Working at the center of chip design efforts, you will collaborate with Architecture, Design, Silicon Validation, Power, and Software teams to bring up systems on the Palladium platform. Daily responsibilities include developing synthesizable monitors, checkers, and stimulus, performing low power testing, and completing detailed test plans. You will develop code for design and verification activities using Verilog, SystemVerilog, and UVM, while building random stimulus infrastructure by reusing existing simulation constraints. Required skills include experience with C/C++ DPI, scripting in Perl, Python, or TCL, and a deep understanding of RTL to Emulation flows involving tools like Veloce, Zebu, or FPGA platforms such as Xilinx and Altera.