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Software Systems Architecture Python XML Perl Interface Design Traceability Verification Validation User Interface Design Project Management +5 more Show less

Electrical Engineering Verilog HDL CPLD FPGA Intel x86 DDR4/5 PCIe g5 Ethernet 100G/ 400G/ 800G Altera Xilinx Cadence Altium Mentor Graphics Signal Integrity Power Integrity EMI/EMC UL CE FCC +14 more Show less

Hardware Design Verilog HDL CPLD FPGA Intel x86 DDR4/5 PCIe g5 Ethernet 100G/ 400G/ 800G Altera Xilinx Cadence Altium Mentor Graphics Signal Integrity Power Integrity EMI/EMC UL CE FCC +14 more Show less

React TypeScript Figma Design Systems Style Dictionary Storybook CI/CD CSS Custom Properties pnpm Turborepo Changesets SemVer React Aria DTCG Design Tokens Monorepos Visual Regression Testing +11 more Show less

React TypeScript Figma Design Systems Style Dictionary Storybook CI/CD Accessibility ARIA CSS Custom Properties pnpm Turborepo Changesets SemVer Radix React Aria DTCG Monorepos Linting +14 more Show less

Datacenter Design Construction Engineering Architecture Site Due Diligence PMP EPC +1 more Show less

ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers +10 more Show less

SystemVerilog C++ Python GPU Architecture RTL Constrained-Random Testing Functional Coverage Computer Architecture Graphics Pipelines 3D Graphics Verification Testbenches Semiconductor Design +7 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling Coherent Interconnects +9 more Show less

Formal Verification SystemVerilog SVA Python C/C++ Perl UVM EDA Tools RTL Computer Architecture Graphics Pipelines Power Gating UPF JIRA Confluence Memory Subsystems +11 more Show less

Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases +12 more Show less

Power Infrastructure Cooling Systems White-space Planning Structured Cabling DCIM AutoCAD Revit PUE TIA-942 EN 50600 Nlyte Sunbird Vertiv +8 more Show less

SoC Design RTL Verilog System Verilog UVM Python Perl Synthesis Physical Design Design Automation DFT CAD Scripting +8 more Show less

SDWAN Cisco Fortinet Juniper Meraki BGP OSPF EIGRP IPSec DMVPN HSRP VRRP GLBP QoS RADIUS TACACS+ SNMP Wireshark SolarWinds FortiManager FortiAnalyzer VoIP SIP PCI DSS HIPAA SOC +21 more Show less

Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating post silicon validation Scripting Micro-architecture +4 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

STA Verilog SystemVerilog ASIC Design Physical Design Spice ECO Timing Analysis Extraction PnR +5 more Show less

SystemVerilog UVM Verilog Python Perl C C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4 +16 more Show less

RTL Verilog SystemVerilog GPU SoC ASIC Synthesis Linting Timing Analysis PPA Microarchitecture Datapath Cache Design Memory Systems +9 more Show less

ASIC Physical Design Floor Planning Synthesis Verilog TCL Perl Python Shell GPU Architecture Timing Constraints Netlist +7 more Show less