AI-Driven ASIC Physical Design Principal Engineer

Cisco

Confirmed live today High trust

Closes in 5 days Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Employment: Full-time
Posted: 64 days ago
Freshness: Confirmed live today
Closes: Nov 1, 2026 (soon)
Nearby: 99+ roles within 25 mi

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Similar $202k

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About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · AI-Driven ASIC Physical Design Principal Engineer

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The AI-Driven ASIC Physical Design Principal Engineer joins the Common Hardware Group to develop innovative hardware platforms for switching, routing, and wireless products. This role focuses on building agentic PnR workflows where Claude autonomously iterates on placement, routing, and timing constraints. You will own the full developer loop, creating RAG pipelines to index internal PDKs and design rule documents while developing prompt architectures to interpret STA timing reports, DRC logs, and congestion maps. Key responsibilities include writing Tcl bridge scripts to translate AI suggestions into executable EDA tool commands. Required expertise includes Python, Docker, and OpenAI APIs like GPT-4o. You must demonstrate proficiency with vector databases such as Pinecone, and experience with tools like Innovus, ICC2, Calibre, and ML-driven placement and routing.

Skills

Python ASIC EDA Tools Innovus ICC2 Calibre Tcl Docker RAG LLM Pinecone Weaviate OpenAI API GPT-4o MLPD RTL2GDSII Tempus Primetime Redhawk Voltus Pegasus

What you'll do

Identify high-value automation targets for timing triage, congestion root-cause analysis, and floorplan suggestions.
Benchmark LLM-generated outputs against ground truth for design quality, timing impact, and sign-off compliance.
Manage the full developer loop from prototyping to evaluation and production to reduce design cycles.
Build agentic PnR workflows where Claude autonomously iterates on placement, routing, and timing constraints.
Create RAG pipelines to index internal PDKs, design rules, sign-off checklists, and runbooks.
Write and maintain Tcl bridge scripts to translate AI suggestions into executable EDA tool commands.
Develop prompt architectures to interpret STA timing reports, DRC logs, congestion maps, and power analysis.

What we're looking for

Bachelor’s degree in Engineering with 15+ years of ASIC experience, Master’s with 12+ years, or PhD with 7+ years.
Experience with Python and leveraging AI tools through accurate prompting to enhance productivity.
Experience building an MCP-based wrapper layer connecting Claude to live EDA tools like Innovus, ICC2, and Calibre.
Experience developing EDA copilots, AI-assisted design tools, and working in Docker or containerized EDA environments.
Experience with ML-driven placement and routing, OpenAI APIs (e.g., GPT-4o, o3), and vector databases like Pinecone or Weaviate.
Experience with RTL2GDSII flow and design tapeouts in 7nm, 5nm, 3nm, or below process technologies (preferred).
Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus (preferred).

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