AI-Driven ASIC Physical Design Principal Engineer

Cisco

Confirmed live 2 days ago High trust

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $250,600–$362,600 / yr
Posted: 18 days ago
Freshness: Confirmed live 2 days ago
Closes: Oct 1, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k

This role $307k

$125k most similar roles pay here $388k

This role pays more than 99% of similar roles. Most pay $175,000–$227,300 — the shaded band above. At the midpoint, this role pays about $307k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · AI-Driven ASIC Physical Design Principal Engineer

Role Posting Log in to save

The AI-Driven ASIC Physical Design Principal Engineer joins the Common Hardware Group to develop innovative hardware platforms for switching, routing, and wireless products. This role focuses on identifying high-value automation targets such as timing triage, congestion root-cause analysis, and floorplan suggestions while managing the full developer loop from prototype to production. The engineer will build agentic PnR workflows where Claude autonomously iterates on placement and routing, create RAG pipelines for internal PDKs and design rules, and develop prompt architectures to interpret STA reports and DRC logs. Key technologies include Python, Docker, and containerized EDA environments. Required skills involve using OpenAI APIs like GPT-4o or o3, vector databases such as Pinecone or Weaviate, and Tcl bridge scripts. The role addresses the technical challenge of accelerating design cycles through machine learning driven placement and routing for advanced silicon.

Skills

Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases

What you'll do

Identify high-value automation targets for timing triage, congestion root-cause analysis, and floorplan suggestions with physical design teams.
Evaluate and benchmark LLM-generated outputs against ground truth for Design QoR, timing impact, and sign-off compliance.
Manage the full developer loop from prototyping to production to achieve measurable reductions in the design cycle.
Build agentic PnR workflows where Claude autonomously iterates on placement, routing, and timing constraints based on tool feedback.
Create RAG pipelines to index internal PDKs, design rules, sign-off checklists, and runbooks for LLM reference.
Write and maintain Tcl bridge scripts to translate AI-suggested fixes into executable EDA tool commands.
Develop prompt architectures to interpret STA timing reports, DRC logs, congestion maps, and power analysis outputs.
Build MCP-based wrapper layers to connect Claude to live EDA tools like Innovus, ICC2, and Calibre for real-time interaction.

What we're looking for

A Bachelor's degree in Engineering with 15+ years of ASIC experience, a Master's with 12+ years, or a PhD with 7+ years is required.
Experience with Python and leveraging AI tools through accurate prompting to enhance productivity is required.
Experience building an MCP-based wrapper layer connecting Claude to live EDA tools like Innovus, ICC2, and Calibre is required.
Experience developing EDA copilots or AI-assisted design tools in Docker and containerized EDA environments is required.
Experience with machine learning driven placement and routing (MLPD / ML-driven PnR) is required.
Experience with OpenAI APIs and vector databases such as Pinecone or Weaviate is required.
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies (preferred).
Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus (preferred).

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