ASIC Design Engineer, STA

Cisco

Confirmed live 3 days ago High trust
Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$155,000–$222,600 / yr
Posted
36 days ago
Freshness
Confirmed live 3 days ago
Closes
Sep 30, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $189k
$142k most similar roles pay here $250k

This role pays less than 52% of similar roles. Most pay $175,000–$227,300 — the shaded band above. At the midpoint, this role pays about $189k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 195 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 195 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · ASIC Design Engineer, STA

Role Posting Log in to save

As an ASIC Design Engineer, STA, you will join the Silicon One team to develop a unified silicon architecture for web scale and service provider networks. You will be responsible for closing timing at block, sub-chip, and full-chip levels while performing quality checks including setup, hold, transition, and noise, alongside handling ECO tasks. Your daily work involves developing extraction and static timing analysis flow, convergence strategies, and ensuring correlation between PNR, Spice, and STA in collaboration with the Physical Design team. You will also create methodologies, guidelines, and checklists to streamline workflows while resolving design and flow issues. The role requires proficiency in Verilog and SystemVerilog programming. This position focuses on solving complex timing challenges within high-performance networking hardware to ensure reliable performance for large-scale infrastructure.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

STA Verilog SystemVerilog ASIC Design Physical Design Spice ECO Timing Analysis Extraction PnR

What you'll do

  • Close timing at block, sub-chip, and full-chip levels.
  • Perform quality checks including setup, hold, transition, and noise.
  • Execute ECO tasks to resolve design issues.
  • Develop extraction and static timing analysis (STA) flow processes.
  • Manage convergence strategies and correlation between PNR, Spice, and STA.
  • Create methodologies, guidelines, and checklists to streamline STA work.
  • Resolve complex design and flow issues to ensure project accuracy.

What we're looking for

  • Bachelor's degree in Electrical or Computer Engineering with 5+ years of ASIC Design experience.
  • Master's degree in Electrical or Computer Engineering with 3+ years of experience.
  • PhD with no years of experience required.
  • Experience with Verilog/SystemVerilog programming.
  • Prior STA experience (preferred).
  • Strong written and verbal communication skills.

Related searches

More ASIC Design Engineer jobs ASIC Design Engineer jobs in San Jose Remote ASIC Design Engineer jobs All jobs at Cisco

More like this

Similar roles

ASIC Design STA Engineer

Amd

San Jose, CA 147 days ago $166,400–$249,600
STA SDC TCL Synopsys Design Compiler PrimeTime RTL Synthesis P&R EDA Tools Spyglass Fishtail Linux QoR Scripting ASIC Design
Hybrid
Save

ASIC Design Engineer

Broadcom

Irvine, CA +1 163 days ago $108,000–$172,800
ASIC Implementation Synthesis Design for Test Floorplanning Place and Route Clock Methodology Power Planning Timing Closure Signal Integrity Physical Design
8+ yrs exp
Save

ASIC Design Engineer

Apple Inc

Santa Clara, CA 119 days ago $129,300–$194,700
ASIC Design RTL Micro-architecture SoC DRAM PHY DFI Simulators System Architecture
Save

ASIC Design Engineer

Nvidia

Santa Clara, CA 26 days ago $116,000–$189,750
RTL Verilog Microarchitecture VLSI Design Logic Synthesis Timing Analysis Python Perl C C++ SoC GPU Digital Systems Computer Architecture Post-Silicon Validation ASIC Design
2+ yrs exp
Save

ASIC Design Engineer

Apple Inc

Santa Clara, CA 144 days ago $150,400–$277,600
ASIC Design RTL Micro-architecture SoC DRAM DFI PHY Simulators System Architecture
3+ yrs exp
Save

ASIC Design Engineer

Apple Inc

Beaverton, OR 144 days ago
Verilog RTL SOC Design Lint CDC Synthesis ECO STA Physical Design Python Perl TCL Microarchitecture Asynchronous Interfaces
10+ yrs exp
Save