Senior ASIC Design Engineer

Cisco

Confirmed live yesterday Trusted

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $167,700–$245,200 / yr
Posted: 29 days ago
Freshness: Confirmed live yesterday
Closes: Oct 1, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k

This role $206k

$134k most similar roles pay here $257k

This role pays more than 64% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $206k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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View all roles at Cisco

At a glance

TL;DR · Senior ASIC Design Engineer

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As a Senior ASIC Design Engineer within the Common Hardware Group, you will contribute to the development of innovative hardware platforms for switching, routing, and wireless products. Your daily responsibilities include authoring design specifications, participating in micro-architecture reviews, and implementing Verilog RTL to meet specific timing, performance, and power requirements. You will analyze functional coverage, collaborate with verification teams to address corner cases, and work with physical design teams to resolve place-and-route issues. Additionally, you will perform diagnostic and post-silicon validation tests in the lab. The role requires proficiency in Verilog and SystemVerilog, along with strong RTL skills regarding timing closure, power, and clock gating. You will apply these skills to solve complex hardware challenges within the silicon and optics space to support infrastructure for the AI era.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating post silicon validation Scripting Micro-architecture

What you'll do

Author design specifications and participate in micro-architecture specification reviews.
Implement Verilog RTL to meet timing, performance, and power requirements.
Develop and analyze functional coverage for designs.
Collaborate with the verification team to address design corner cases and close coverage.
Work with the physical design team to resolve timing and place-and-route issues.
Perform diagnostic and post-silicon validation tests in the lab.

What we're looking for

Bachelor's degree in Electrical or Computer Engineering with 7+ years of ASIC Design experience.
Master's degree in Electrical or Computer Engineering with 4+ years of ASIC Design experience.
PhD in Electrical or Computer Engineering with 1 year of ASIC Design experience.
Experience with Verilog and System Verilog.
At least one full ASIC tapeout (advanced nodes preferred).
Strong RTL skills with command of timing closure, power, clock gating, and the full ASIC design flow (preferred).
Solid debug and scripting skills (preferred).
Good written and verbal communication skills (preferred).

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