Senior ASIC Design Engineer

Cisco

Confirmed live yesterday Trusted

Closes in 5 days

Quick summary

Work type: On-site
Location: San Jose, CA
Employment: Full-time
Posted: 75 days ago
Freshness: Confirmed live yesterday
Closes: Nov 1, 2026 (soon)
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $192k

$136k $232k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $167,737–$216,250.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer

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The Senior ASIC Design Engineer joins the Common Hardware Group to develop innovative hardware platforms for switching, routing, and wireless products. In this role, you will author design specifications, participate in micro-architecture reviews, and implement Verilog RTL to meet specific timing, performance, and power requirements. Your daily responsibilities include developing and analyzing functional coverage, collaborating with verification teams to address design corner cases, and working with physical design teams to resolve place-and-route issues. You will also perform diagnostic and post-silicon validation tests in a lab environment. The position requires proficiency in Verilog and System Verilog, along with strong RTL skills regarding timing closure, power, and clock gating. This work focuses on creating silicon and hardware platforms that power core networking infrastructure.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating Post Silicon Validation Scripting Micro-architecture Place-and-Route Functional Coverage

What you'll do

Author design specifications and participate in micro-architecture specification reviews.
Implement Verilog RTL to meet timing, performance, and power requirements.
Develop and analyze functional coverage for designs.
Address design corner cases and close coverage with the verification team.
Work with the physical design team to close timing and place-and-route issues.
Perform diagnostic and post-silicon validation tests in the lab.

What we're looking for

Bachelor’s degree in Electrical or Computer engineering with 7+ years of ASIC Design related experience.
Master’s degree in Electrical or Computer engineering with 4+ years of ASIC Design related experience.
PhD in Electrical or Computer engineering with 1 year of ASIC Design related experience.
Experience with Verilog/System Verilog.
At least one full ASIC tapeout, preferably on advanced nodes (preferred).
Strong RTL skills with command of timing closure, power, clock gating, and the full ASIC design flow (preferred).
Solid debug and scripting skills (preferred).
Good written and verbal communication skills (preferred).

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