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CPU Microarchitecture Performance Modeling Cycle-accurate Simulators C++ Python Workload Analysis Performance Profiling power, and area trade-offs Software Engineering Practices +4 more Show less

RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution +7 more Show less

VLSI RTL Design Verilog HDL Cache Architecture CPU Coherency NoC SoC Scripting Microarchitecture Timing Closure Design for Test Physical Design Routing Fabric +8 more Show less

CPU Microarchitecture Performance Modeling System Architecture Hardware Performance Counters NUMA TLB PCIe CXL HBM DDR data-analysis Scripting Virtualization HPC Power Modeling ISA Telemetry Bottleneck Analysis +13 more Show less

RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution +6 more Show less

Verilog SystemVerilog VHDL RTL Design LLM Agentic AI Simulation Waveform Debug Logic Design Synthesis CPU Architecture Microarchitecture Hardware Engineering +8 more Show less

RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulation Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems Power and Area Tradeoffs +10 more Show less

RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulators Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems +9 more Show less

RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulation Waveform Debugging CPU Architecture +6 more Show less

RTL Verilog VHDL C C++ Python Perl Microarchitecture Formal Verification Simulation Emulation Out-of-Order Execution Branch Prediction +8 more Show less

RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling +10 more Show less

RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling +10 more Show less

RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Load/Store Execution +10 more Show less

RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Waveform Debugging +10 more Show less

RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Cache Memory Subsystems Waveform Debugging +12 more Show less

RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling Load/Store Execution +11 more Show less

RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Logic Design Waveform Debugging +9 more Show less

RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing +12 more Show less

RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management Clock Generation Asynchronous Clock Crossing +13 more Show less

RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing Power Integrity +13 more Show less