CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
—
Salary
$184,700–$324,800 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $217k
This role $255k
$147k most similar roles pay here $344k

This role pays more than 88% of similar roles. Most pay $184,900–$250,000 — the shaded band above. At the midpoint, this role pays about $255k versus about $217k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · CPU Microarchitect/RTL Engineer, Execution, Load/Store

The CPU Microarchitect/RTL Engineer - Execution, Load/Store joins the Silicon Engineering Group to drive architecture and RTL development for performant cores focusing on integer, floating-point, and load/store execution. This role involves micro-architecture development from high-level exploration through detailed specification, alongside RTL ownership to meet power, performance, area, and timing goals. The engineer will participate in verification support via test bench development and formal methods, conduct performance exploration and correlation, and collaborate on physical design implementation. Required skills include microprocessor architecture knowledge, logic design principles, Verilog or VHDL, and experience with simulators and waveform debugging. Preferred qualifications include expertise in out-of-order execution, instruction scheduling, cache subsystems, and low power techniques, along with proficiency in C, C++, Perl, or Python to solve complex hardware challenges within the high-performance microprocessor domain.

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