CPU RTL/AI Micro-Architect - AI Development

Qualcomm

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$179,000–$268,400 / yr
Posted
9 days ago
Closes
Nov 28, 2026

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $224k
$149k most similar roles pay here $281k

This role pays more than 65% of similar roles. Most pay $162,000–$239,137 — the shaded band above. At the midpoint, this role pays about $224k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 660 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

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At a glance

TL;DR · CPU RTL/AI Micro-Architect - AI Development

As a Senior AI-Enhanced RTL Developer at Qualcomm Technologies, Inc., you will join the cutting-edge team driving innovation in high-performance CPU architecture for datacenter workloads. Your primary responsibilities include extending internal AI tools to enhance RTL design productivity and developing AI-driven capabilities for code review, quality analysis, and automated debug acceleration. You will also integrate AI into standard RTL development loops and enable early-stage insights for timing, power, and area tradeoffs. This role involves collaborating with CAD, DV, and global design teams to scale AI-enabled workflows across programs and geographies while ensuring alignment with Qualcomm’s established RTL principles of readability, maintainability, and cross-discipline usability. The ideal candidate has strong knowledge in AI/LLM-based engineering tools, experience with Verilog/SystemVerilog RTL design, and a solid understanding of CPU design techniques including logic design principles and low-power microarchitecture methods.

What you'll do

  • Apply AI tools to enhance RTL design productivity.
  • Develop AI-driven capabilities for RTL code review and quality analysis.
  • Enable AI-assisted analysis for timing, power, and area tradeoffs.
  • Integrate AI into existing toolchains like linting and synthesis.
  • Scale AI-enabled workflows across global design teams and programs.

What we're looking for

  • Experience in AI/LLM-based engineering tools for agentic development and agent orchestration.
  • Proficient in Verilog/SystemVerilog RTL design and simulation tools.
  • Knowledge of CPU design techniques including logic design principles and low-power microarchitecture.
  • Ability to integrate AI into standard RTL development workflows and toolchains.
  • Strong background in timing, power, and area (PPA) analysis for microarchitectural optimization.
  • Experience in developing mechanisms for early-stage actionable insights in the design cycle.
  • Expertise in enhancing RTL code quality through automated review and debug acceleration.

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