CPU Microarchitect/RTL Engineer

The CPU Microarchitect/RTL Engineer joins the Silicon Engineering Group to drive architecture and RTL development for next-generation CPUs. This role involves microarchitecture development and specification, ranging from high-level exploration to detailed technical specifications. The engineer will own RTL features to meet specific power, performance, area, and timing goals while supporting test bench development and simulation for functional and performance verification. Key responsibilities include performing performance exploration and correlation to ensure designs meet targets while collaborating with multifunctional teams on physical design implementation. Candidates must possess experience in microprocessor architecture and proficiency in Verilog or VHDL. Preferred skills include knowledge of logic design principles, expertise in areas like branch prediction or out-of-order execution, and experience using Perl, Python, or Verdi for waveform debugging to solve complex high-performance, low-power microarchitecture challenges.