CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$150,400–$277,600 / yr
Posted
15 days ago
Freshness
Confirmed live 2 days ago

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $217k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 52% of similar roles. Most pay $184,900–$250,000 — the shaded band above. At the midpoint, this role pays about $214k versus about $217k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · CPU Microarchitect/RTL Engineer, Execution, Load/Store

The CPU Microarchitect/RTL Engineer - Execution, Load/Store joins the Silicon Engineering Group to drive architecture and RTL development for performant cores. This role involves micro-architecture development and specification from early exploration through detailed research, alongside ownership of RTL design to meet specific power, performance, area, and timing goals. The engineer will also support verification teams with test bench development and formal methods while performing performance exploration and correlation to ensure designs meet targets. Key responsibilities include collaborating with multi-functional teams on physical design implementation for reliability and testability. Required skills include experience in microprocessor architecture, logic design principles, Verilog or VHDL, and waveform debugging. Preferred expertise includes out-of-order execution, instruction scheduling, cache subsystems, low power techniques, C/C++ programming, and scripting in Perl or Python to solve complex processor performance challenges.

What you'll do

  • Develop and specify micro-architecture from high-level exploration through detailed technical specifications.
  • Own the development, assessment, and refinement of RTL design to meet power, performance, area, and timing goals.
  • Support verification teams with test bench development, formal methods, and simulation or emulation for functional verification.
  • Explore high-performance strategies and correlate results with performance verification teams to ensure designs meet targets.
  • Collaborate with multi-functional teams to implement physical design aspects including reliability, testability, and power.
  • Implement advanced features such as out-of-order execution, instruction scheduling, and load/store subsystems.

What we're looking for

  • Minimum BS degree and 3+ years of relevant industry experience.
  • Experience with microprocessor architecture.
  • Experience with logic design principles involving timing and power implications.
  • Experience in Verilog or VHDL.
  • Experience with simulators and waveform debugging processes.
  • Expertise in out-of-order execution, instruction scheduling, integer/floating-point, load/store, cache, or memory subsystems (preferred).
  • Understanding of low power microarchitecture techniques and high-performance trade-offs (preferred).
  • Experience in C, C++, Perl, or Python (preferred).

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