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UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD +5 more Show less

Python ASIC Verification Design CI/CD

Python ASIC Verification CI/CD

Python ASIC Verification CI/CD

AXI AHB RTL FPGA ASIC

AXI AHB RTL FPGA ASIC

AXI AHB RTL FPGA ASIC

Python ASIC verification Test bench development

Python ASIC Design Verification Test Bench Development CI/CD

Python ASIC Verification

AXI AHB RTL FPGA ASIC

AXI AHB RTL FPGA ASIC

AXI AHB RTL FPGA ASIC

RTL FPGA ASIC AXI AHB VHDL Verilog SystemC Cadence Synopsys Xilinx Altera Mentor Graphics JTAG UVM Linux Git CI/CD Python Matlab +15 more Show less

Python ASIC verification FPGA design Test bench development Digital ASIC verification System level testing Code coverage Functional coverage CI/CD +4 more Show less

ASIC STA Hyperscale hierarchical analysis parasitic stitching IO budgeting flat parasitic extraction timing constraints timing closure ECO on-chip variation AOCV POCV voltage temperature aging-based timing derates Synopsys DC/DCG/FC Formality Cadence LEC Star-RCXT Quantus Synopsys Primetime Tempus TCL Perl Python +21 more Show less

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Exceptions Async_Boundaries HDL Digital_Design_Concepts +11 more Show less

Synopsys DC/DCG/FC Formality Cadence LEC Star-RCXT Quantus Primetime PTPX Tweaker PrimeClosure Tempus TCL Perl Python Static Timing Analysis Parasitic Extraction Timing Closure On-Chip Variation Scripting +14 more Show less

Verilog SystemVerilog

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Constraints Full_Chip_Design Block_Level_Design RTL_Implementation Digital_Design_Concepts +12 more Show less