ASIC STA Engineer

Cisco

Remote

Quick summary

Work type: Remote
Location: Maynard, MA
Salary: $135,800–$195,100 / yr
Posted: 53 days ago
Closes: Jul 3, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k

This role $165k

$125k most similar roles pay here $236k

This role pays less than 72% of similar roles. Most pay $165,112–$216,250 — the shaded band above. At the midpoint, this role pays about $165k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC STA Engineer

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As an ASIC Design Engineer on the STA team at Cisco, you will contribute to the development of extraction and static timing analysis (STA) flow, focusing on convergence strategies and correlation between physical design rules, Spice simulations, and STA processes. Your responsibilities include creating methodologies, guidelines, and checklists to enhance efficiency in STA work, resolving complex design and flow issues, and driving execution to ensure accuracy and progress. The role requires a strong background in electrical or computer engineering with experience in Verilog/SystemVerilog programming, ideally complemented by prior STA experience and excellent communication skills. This position is integral to the development of cutting-edge semiconductor solutions for large-scale enterprise applications.

Skills

Verilog SystemVerilog

What you'll do

Develop methodologies and guidelines for static timing analysis (STA) flow.
Resolve complex design and flow issues in STA processes.
Ensure accuracy and progress in STA execution through rigorous testing.
Enhance correlation between physical implementation, Spice simulation, and STA.
Streamline the extraction process to improve overall efficiency.

What we're looking for

Bachelor’s degree in Electrical or Computer Engineering with 5+ years of ASIC design experience.
Master's degree in Electrical or Computer Engineering with 3+ years of relevant experience.
PhD in Electrical or Computer Engineering with any level of professional experience.
Experience with Verilog/SystemVerilog programming.
Development of methodologies, guidelines, and checklists for STA work.

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