Lead ASIC Design Verification Engineer (Starshield Satellite Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Hawthorne, CA
Salary: $160,000–$225,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $169k

This role $192k

$127k most similar roles pay here $236k

This role pays more than 62% of similar roles. Most pay $137,500–$201,250 — the shaded band above. At the midpoint, this role pays about $192k versus about $169k for comparable roles.

Based on 239 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Lead ASIC Design Verification Engineer (Starshield Satellite Engineering)

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The Lead ASIC Design Verification Engineer will lead a team responsible for custom ASICs and FPGAs design verification in satellite systems, ensuring high performance and reliability. This role involves overseeing test plan execution, regression testing, and coverage closure at both block and system levels. The engineer will collaborate with cross-functional teams to drive product requirements and enhance the capabilities of Starshield satellites, which process vast amounts of data for national security applications. Essential skills include experience in design verification and test bench development, proficiency in Python for automation, and a background in electrical or computer engineering. This position demands expertise in digital ASIC verification and leadership in recruiting and developing top-tier talent to support cutting-edge satellite technology.

Skills

Python ASIC verification FPGA design Test bench development Digital ASIC verification System level testing Code coverage Functional coverage CI/CD

What you'll do

Lead the verification of digital ASICs at block and system levels.
Oversee test plan execution, regression runs, and coverage closure for code and functionality.
Collaborate with engineering leaders to define product requirements and enhance satellite performance.
Develop and train a team of engineers to ensure high-quality chip design and operation.
Recruit top talent to strengthen the engineering organization's capabilities.

What we're looking for

Bachelor’s degree in electrical engineering, computer engineering, or related field.
4+ years of experience in design verification and test bench development.
Proficiency in Python for automation tasks.
Experience leading a team in digital ASIC verification at block and system levels.
Ability to recruit, develop, train, and retain top-tier engineering talent.

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