Sr. ASIC Design Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $160,000–$225,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $169k

This role $192k

$124k most similar roles pay here $236k

This role pays more than 64% of similar roles. Most pay $135,000–$202,850 — the shaded band above. At the midpoint, this role pays about $192k versus about $169k for comparable roles.

Based on 239 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. ASIC Design Engineer (Starshield)

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As a Sr. ASIC Design Engineer at Starshield in Irvine, CA, you will join the National Security team to work on cutting-edge FPGA and ASIC development projects. Your primary responsibilities include RTL implementation, AXI interface design, and collaborating with cross-functional teams to ensure high-quality chip designs meet stringent performance requirements. Ideal candidates possess 5+ years of experience in RTL implementation or FPGA/ASIC development, along with expertise in Verilog/SystemVerilog, and a solid understanding of AXI, AHB protocols. This role demands strong problem-solving skills and the ability to work within ITAR compliance guidelines on projects that address significant national security challenges at scale.

Skills

AXI AHB RTL FPGA ASIC

What you'll do

Design and implement complex RTL for FPGA/ASIC development.
Develop and optimize system interfaces using AXI, AHB protocols.
Collaborate on verification of ASIC designs through simulation and testing.
Troubleshoot and debug issues in hardware design and implementation.
Ensure compliance with ITAR regulations for national security projects.

What we're looking for

5+ years of experience in RTL implementation and FPGA/ASIC development.
Proficiency in AXI, AHB, and other bus protocols.
Strong understanding of ITAR requirements for U.S. Department of State compliance.
Experience with ASIC design and verification methodologies.
Bachelor’s or Master’s degree in Electrical Engineering or Computer Science.
Excellent problem-solving skills and ability to work on complex projects.

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