ASIC Engineering Technical Leader- STA

Cisco

Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$210,600–$305,100 / yr
Posted
36 days ago
Closes
Jul 9, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k
This role $258k
$147k most similar roles pay here $322k

This role pays more than 95% of similar roles. Most pay $177,250–$223,700 — the shaded band above. At the midpoint, this role pays about $258k versus about $200k for comparable roles.

Based on 239 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Engineering Technical Leader- STA

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Join Cisco’s advanced engineering team as a senior ASIC design engineer where you will define and oversee the architecture of high-performance ASICs for deployment across various platforms. Your daily tasks include driving innovative verification strategies, creating guidelines and standards, and directing mixed-signal teams to ensure technical specifications are met. You will work with Synopsys tools like DC/DCG/FC, Formality, Star-RCXT, and Cadence Tempus for static timing analysis, while also managing complex issues through vendor interfaces and design leads. With a minimum of 10 years of experience in ASIC development and expertise in STA, hierarchical analysis, and timing closure, you will contribute to the creation of high-volume, quality products that solve critical business challenges at scale.

Skills

Synopsys DC/DCG/FC Formality Cadence LEC Star-RCXT Quantus Primetime PTPX Tweaker PrimeClosure Tempus TCL Perl Python Static Timing Analysis Parasitic Extraction Timing Closure On-Chip Variation Scripting

What you'll do

  • Oversees the definition and architecture of high-performance ASICs.
  • Determines methodology for creating and reusing code in design processes.
  • Creates innovative verification strategies for complex designs.
  • Directs mixed-signal teams to define requirements and ensure specifications are met.
  • Interfaces with vendors and leads on complex issues, driving technology rules.
  • Oversees physical design functions, providing expertise in highly complex scenarios.
  • Reviews IC designs and recommends improvements for analog/mixed-signal circuits.

What we're looking for

  • 10+ years of experience in ASIC design and verification.
  • Expertise in static timing analysis (STA) for hierarchical designs.
  • Experience with timing closure techniques across various process nodes.
  • Proficiency in on-chip variation management and derating strategies.
  • Knowledge of synthesis tools like Synopsys Design Compiler.
  • Skills in formal verification using Synopsys, Formality, or Cadence LEC.
  • Experience with parasitic extraction tools such as Synopsys Star-RCXT.

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