Sr. ASIC Design Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Palo Alto, CA
Salary: $170,000–$235,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $169k

This role $202k

$123k most similar roles pay here $247k

This role pays more than 75% of similar roles. Most pay $135,000–$202,850 — the shaded band above. At the midpoint, this role pays about $202k versus about $169k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. ASIC Design Engineer (Starshield)

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As a Senior ASIC Design Engineer at Starshield in Palo Alto, CA, you will join a specialized team focused on national security projects. Your primary responsibilities include designing and implementing complex RTL (Register Transfer Level) circuits for FPGA/ASIC development, ensuring compliance with AXI, AHB, and other industry standards. You will work closely with hardware architects to create scalable and secure solutions that address critical business challenges in the defense sector. The ideal candidate possesses extensive experience in ASIC design and a strong background in digital logic design, verification methodologies, and scripting languages such as Python or Perl. Familiarity with ITAR regulations is essential due to the sensitive nature of the work.

Skills

AXI AHB RTL FPGA ASIC

What you'll do

Design and implement complex RTL for ASIC development.
Optimize FPGA/ASIC designs for performance, power, and area efficiency.
Develop verification plans and test benches for design validation.
Collaborate on debugging and resolving issues in hardware designs.
Integrate IP blocks using AXI, AHB, and other standard protocols.

What we're looking for

5+ years of experience in RTL implementation and FPGA/ASIC development.
Proficiency in AXI, AHB, and other bus protocols.
Strong understanding of ASIC design methodologies.
Experience with ITAR compliance for national security projects.
Bachelor’s degree or higher in Electrical Engineering, Computer Science, or related field.

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