Manager, ASIC Design Engineering

SpaceX

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Hawthorne, CA
Salary
$190,000–$245,000 / yr
Posted
179 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $218k
$146k $256k
below market most similar roles pay here above market

This role pays more than 69% of similar roles. Most pay $177,250–$227,500 — the blue band above. At the midpoint, this role pays about $218k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Manager, ASIC Design Engineering

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The Manager, ASIC Design Engineering leads a team developing ASICs and FPGAs for Starshield satellite systems, which provide earth observation, communications, and hosted payloads for national security. This role involves leading architectural trades, deriving specifications, and defining micro-architecture for high-speed data systems. Key responsibilities include implementing RTL in Verilog or System Verilog, managing top-level integration, providing timing constraints, and supporting physical implementation tasks like synthesis and timing closure. The manager must also oversee silicon bring-up, validation, and automated test lab equipment development. Required technical skills include RTL implementation, FPGA/ASIC development, and experience with standard bus protocols like AXI or AHB. Candidates should be proficient with EDA tools such as VCS, Questa, Spyglass, and Xilinx Vivado, while utilizing scripting languages like Python and TCL.

Skills

ASIC Design FPGA Verilog System Verilog RTL Synthesis Timing Closure Python TCL VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II AXI AHB DSP RFIC Embedded Processors

What you'll do

  • Lead a team responsible for the digital design of ASICs and FPGAs for Starshield projects.
  • Lead architectural trades for features, performance requirements, and system limitations to derive subsystem specifications.
  • Define micro-architecture and implement RTL in Verilog or System Verilog for top-level integration.
  • Deliver fully verified, synthesis, and timing-clean designs in coordination with the verification team.
  • Provide timing constraints and support the physical implementation team with synthesis and timing closure.
  • Participate in silicon bring-up, validation, and the development of automated test lab equipment.
  • Recruit, develop, train, and retain high-performing engineering team members.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, computer science, or another engineering discipline.
  • 5+ years of experience in RTL implementation and/or FPGA/ASIC development.
  • 2+ years of experience with direct report management or mentoring an engineering team.
  • Experience solving problems including clock domain crossings and power optimization (preferred).
  • Experience developing complex ASICs (preferred).
  • Experience with multicore CPU subsystem design (preferred).
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.) (preferred).
  • Experience with embedded processors (preferred).
  • Experience with high speed and low power design techniques (preferred).
  • Scripting skills (Python, TCL etc.) (preferred).
  • Experience with EDA tools such as HDL simulators, HDL Lint tools, and FPGA tools (preferred).
  • Ability to work long hours and weekends as necessary to support critical milestones.
  • Willingness to travel for off-site testing.
  • Applicant must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.

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