Manager, ASIC Design Engineering

SpaceX

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Hawthorne, CA
Salary
$190,000–$245,000 / yr
Posted
133 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k
This role $218k
$149k most similar roles pay here $255k

This role pays more than 70% of similar roles. Most pay $177,250–$229,575 — the shaded band above. At the midpoint, this role pays about $218k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Manager, ASIC Design Engineering

Role Posting Log in to save

Manager, ASIC Design Engineering (Starshield Silicon) leads a team developing ASICs and FPGAs for satellite systems designed for government use in earth observation, communications, and hosted payloads. The manager oversees the full lifecycle from initial design to on-orbit operations, including architectural trades, defining micro-architecture, and implementing RTL in Verilog or System Verilog. Key responsibilities involve collaborating with verification teams, providing timing constraints for physical implementation, and participating in silicon bring-up and validation. The role requires expertise in high-speed and low-power design techniques, multicore CPU subsystem design, and standard bus protocols like AXI or AHB. Candidates should be proficient with EDA tools such as VCS, Questa, Spyglass, Vivado, or Quartus II, along with scripting skills in Python or TCL to solve complex problems like clock domain crossings and power optimization for advanced satellite hardware.

Skills

ASIC FPGA Verilog System Verilog RTL Synthesis Timing Closure AXI AHB Python TCL VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II

What you'll do

  • Lead a team responsible for the digital design of ASICs and FPGAs for Starshield projects.
  • Conduct architectural trades for features, performance requirements, and system limitations to derive subsystem specifications.
  • Define micro-architecture and implement RTL in Verilog or System Verilog for top-level integration.
  • Collaborate with verification teams to ensure all aspects of the design are fully covered and verified.
  • Provide timing constraints and support physical implementation tasks like synthesis and timing closure.
  • Participate in silicon bring-up, validation, and the development of automated test lab equipment.
  • Recruit, develop, train, and retain high-performing engineering team members.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, computer science, or another engineering discipline.
  • 5+ years of experience in RTL implementation and/or FPGA/ASIC development.
  • 2+ years of experience with direct report management or mentoring an engineering team.
  • Experience with high speed and low power design techniques including clock domain crossings and power optimization.
  • Proficiency in Verilog or System Verilog for micro-architecture and RTL implementation.
  • Experience with standard bus protocols, multicore CPU subsystem design, and embedded processors.
  • Proficiency with EDA tools such as HDL simulators, lint tools, and FPGA tools.
  • Must be a U.S. citizen, national, permanent resident, or eligible for export control authorizations.

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