Manager, ASIC Design Engineering (Starshield Silicon)

SpaceX

Quick summary

Work type: On-site
Location: Hawthorne, CA
Salary: $190,000–$245,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $204k

This role $218k

$154k most similar roles pay here $255k

This role pays more than 64% of similar roles. Most pay $170,000–$237,550 — the shaded band above. At the midpoint, this role pays about $218k versus about $204k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Manager, ASIC Design Engineering (Starshield Silicon)

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The Manager of ASIC Design Engineering at Starshield Silicon will lead a team developing advanced ASICs and FPGAs for cutting-edge satellite systems, delivering unparalleled data throughput to military personnel. This role involves daily oversight of digital design processes from conception through on-orbit operations, including architectural trade-offs and collaboration with cross-functional engineering teams to enhance performance. The ideal candidate has extensive experience in RTL implementation and FPGA/ASIC development, alongside proven leadership skills in managing or mentoring engineers. Proficiency in technologies such as AXI and AHB is essential for this position, which operates at the forefront of satellite technology to ensure national security.

Skills

RTL FPGA ASIC AXI AHB VHDL Verilog SystemC Cadence Synopsys Xilinx Altera Mentor Graphics JTAG UVM Linux Git CI/CD Python Matlab

What you'll do

Lead the digital design of ASICs and FPGAs for Starshield satellite projects.
Conduct architectural trades to balance features, performance, and system constraints.
Collaborate with engineering leaders to enhance product requirements and performance.
Recruit, develop, and retain top-tier engineers for high-performance chip development.
Manage a team responsible for the design, manufacturing, testing, and operation of chips.

What we're looking for

Bachelor’s degree in electrical engineering, computer engineering, or related field.
5+ years of experience in RTL implementation and FPGA/ASIC development.
2+ years of direct report management or team mentoring experience.
Proven ability to lead architectural trades for system performance requirements.
Experience recruiting, developing, training, and retaining top-tier engineering talent.

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