Sr. ASIC Design Verification Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $160,000–$225,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $175k

This role $192k

$128k most similar roles pay here $235k

This role pays more than 59% of similar roles. Most pay $138,300–$211,475 — the shaded band above. At the midpoint, this role pays about $192k versus about $175k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. ASIC Design Verification Engineer (Starshield)

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The Sr. ASIC Design Verification Engineer role at Starshield in Irvine, CA involves working on advanced national security projects within a specialized engineering team. This senior-level position focuses on developing and maintaining verification environments for complex ASIC designs using Python for automation. Daily tasks include creating testbenches, writing scripts to automate design validation processes, and collaborating with hardware engineers to ensure robust system functionality. Candidates should possess expertise in digital design verification methodologies, experience with EDA tools like Cadence or Synopsys, and a strong background in C/C++ alongside Python scripting. The role demands an understanding of large-scale semiconductor projects and the ability to tackle intricate verification challenges within a highly regulated ITAR environment.

Skills

Python ASIC Verification Design CI/CD

What you'll do

Develop and execute verification plans for complex ASIC designs.
Create testbenches using SystemVerilog/UVM to validate design functionality.
Write scripts in Python to automate testing processes and improve efficiency.
Analyze simulation results, debug issues, and report findings to the team.
Collaborate on defining coverage metrics and ensuring comprehensive verification.

What we're looking for

5+ years of experience in ASIC design verification
Proficient in Python for automation and scripting
Strong knowledge of verification methodologies and tools
Experience with UVM/OVM verification environments
Bachelor’s degree in Electrical Engineering, Computer Science or related field
ITAR eligibility and ability to obtain security clearance

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