ASIC Design Hardware Engineer - SDC/STA (Hybrid)

Cisco

Hybrid Actively hiring
San Jose, CA Posted 23 days ago $152,500–$219,200 / year
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At a glance

AI generated

TL;DR

As a Design/SDC Engineer at Cisco Silicon One in San Jose, CA, you will join a dynamic team of ASIC experts working on cutting-edge silicon architecture for web-scale and service provider networks. Your primary responsibilities include developing timing constraints at both block level and full-chip, validating them using tools like TCM and Timevision, and collaborating with front-end and back-end teams to refine design and timing constraints. You will also contribute to the development of methodologies that promote efficient SDC transitions from block to full-chip levels and vice versa, ensuring correctness and quality throughout the design cycle. The role requires proficiency in Synopsys DC/FC, STA tools like Primetime, Verilog/SystemVerilog, and scripting languages such as Shell, Perl, and TCL. This position offers a unique blend of startup culture and large-scale resources within Cisco’s extensive silicon organization, providing ample opportunities for growth and innovation in the realm of next-generation networking chips.

Skills

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Exceptions Async_Boundaries HDL Digital_Design_Concepts

What you'll do

  • Develop block level and full-chip SDCs for ASIC design.
  • Collaborate with physical design and DFT teams to close full-chip timing in multiple modes.
  • Work with design/architecture teams to understand clocking structure and develop timing constraints.
  • Help refine methodologies for promoting block-level SDCs to full-chip and vice versa.
  • Validate timing constraints using industry-standard verification tools before releasing them for physical design.

What we're looking for

  • Bachelor’s Degree in Electrical or Computer Engineering with 4+ years of ASIC experience or Master’s with 2+ years.
  • Proficient in Synopsys DC/DCG/FC synthesis tools and STA tools like Primetime.
  • Strong knowledge of Verilog/SystemVerilog and scripting languages (Shell, Perl, TCL).
  • Experience developing block/full-chip SDCs for functional and test modes.
  • Deep understanding of digital design concepts including clocking and timing exceptions.

Market check

Salary context

This $152,500–$219,200 range sits above 46% of similar postings on FindRole.

Peer median band

$152,200–$228,000

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$158,850–$216,562

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 103 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 103 roles with salary data.

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