ASIC Design Hardware Engineer - SDC/STA (Hybrid)

Cisco

Hybrid Actively hiring
San Jose, CA Posted 65 days ago Apply by Jun 26, 2026 $165,000–$241,400 / year
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At a glance

AI generated

TL;DR

As a Design/SDC Engineer at Cisco Silicon One in San Jose, CA, you will join a dynamic team of ASIC experts working on cutting-edge silicon architecture for web-scale and service provider networks. Your primary responsibilities include developing timing constraints at both block level and full-chip, validating them using tools like TCM and Timevision, and collaborating with front-end and back-end teams to ensure seamless physical design closure. You will also contribute to the development of methodologies that promote efficient SDC transitions between block and full-chip levels, ensuring correctness and quality throughout the design cycle. The role requires proficiency in Synopsys DC/FC, STA tools like Primetime, Verilog/SystemVerilog, and scripting languages such as Shell, Perl, and TCL, along with a deep understanding of digital design concepts including clocking structures and timing exceptions. This position offers an unparalleled opportunity to work on next-generation networking chips within a large-scale organization that fosters both startup culture and extensive growth opportunities.

Skills

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Constraints Full_Chip_Design Block_Level_Design RTL_Implementation Digital_Design_Concepts

What you'll do

  • Develop block level and full-chip SDCs for ASIC design.
  • Validate timing constraints using industry-standard verification tools before physical design release.
  • Collaborate with front-end and back-end teams to refine design and timing constraints.
  • Contribute to the development of methodologies for efficient SDC promotion and validation.
  • Review block-level SDCs and clocking diagrams, collaborating on SDC development with RTL designers.

What we're looking for

  • Bachelor’s Degree in Electrical or Computer Engineering with 6+ years of ASIC experience or Master’s with 4+ years.
  • Proficient in Synopsys DC/DCG/FC synthesis tools and Primetime STA tool.
  • Strong knowledge of HDL (Verilog/SystemVerilog) and scripting languages like Shell, Perl, TCL.
  • Experience developing block/full-chip SDCs for functional and test modes.
  • Deep understanding of digital design concepts including clocking, timing exceptions.

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $203k
$141k most similar roles pay here $252k

This role pays more than 60% of similar roles. Most pay $157,800–$216,250 — the shaded band above. At the midpoint, this role pays about $203k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 121 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 121 roles with salary data.

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