Sr. ASIC Design Verification Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Palo Alto, CA
Salary: $170,000–$235,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $175k

This role $202k

$127k most similar roles pay here $247k

This role pays more than 70% of similar roles. Most pay $138,300–$211,475 — the shaded band above. At the midpoint, this role pays about $202k versus about $175k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. ASIC Design Verification Engineer (Starshield)

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As a Senior ASIC Design Verification Engineer at Starshield in Palo Alto, CA, you will join a dedicated team focused on national security to develop cutting-edge hardware solutions. Your primary responsibilities include designing and implementing verification strategies for complex ASICs, automating test processes with Python, and ensuring the reliability of high-performance computing systems. You will work closely with design engineers to define verification plans, create testbenches, and execute simulations to validate designs against stringent requirements. The ideal candidate possesses expertise in digital logic design, verification methodologies like UVM, and familiarity with EDA tools such as Cadence or Synopsys. This role demands a deep understanding of security protocols and the ability to handle projects at scale within a highly regulated environment.

Skills

Python ASIC Verification CI/CD

What you'll do

Develop and execute verification plans for complex ASIC designs.
Create testbenches, simulations, and validation scripts to ensure design integrity.
Identify and debug issues in hardware logic using advanced verification methodologies.
Collaborate on the development of custom verification IP (VIP) components.
Automate verification processes using Python scripting for efficiency.

What we're looking for

Extensive experience in ASIC design verification required.
Proficiency in Python for automation and scripting essential.
Strong background in creating testbenches and verification environments.
Experience with verification methodologies such as UVM/OVM preferred.
Knowledge of digital design and verification tools like VCS, Questa is necessary.
ITAR compliance requirements must be met for security clearance.

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