Senior ASIC Design Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Hawthorne, CA
Salary
$160,000–$225,000 / yr
Posted
163 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $192k
$151k most similar roles pay here $244k

This role pays less than 54% of similar roles. Most pay $176,687–$223,175 — the shaded band above. At the midpoint, this role pays about $192k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer

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Sr. ASIC Design Engineer (Starshield) joins the Starshield team to develop next-generation FPGAs and ASICs for space and ground infrastructures supporting national security efforts in earth observation, communications, and hosted payloads. The role involves designing digital ASICs and FPGAs, evaluating architectural trade-offs, defining micro-architecture, and implementing RTL using Verilog or System Verilog. You will collaborate with verification teams to ensure design coverage, provide timing constraints for physical implementation, and participate in silicon bring-up and validation. Key technical requirements include experience with multicore CPU subsystems, standard bus protocols like AXI and AHB, high speed and low power design techniques, and scripting in Python or TCL. Proficiency with EDA tools such as VCS, Questa, Spyglass, Vivado, and Quartus II is required to solve complex problems involving clock domain crossings and power optimization.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

ASIC FPGA Verilog System Verilog RTL Python TCL AXI AHB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Synthesis Timing Closure Formality

What you'll do

  • Design digital ASICs and FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on performance requirements and system limitations.
  • Derive subsystem specifications and partition functions between hardware and software domains.
  • Implement RTL in Verilog or System Verilog to deliver synthesis and timing clean designs.
  • Provide timing constraints and support the physical implementation team with synthesis and timing closure.
  • Collaborate with verification teams to ensure all design aspects are fully covered.
  • Participate in silicon bring-up, validation, and the development of automated test equipment.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in RTL implementation and/or FPGA/ASIC development.
  • Experience with high speed and low power design techniques.
  • Proficiency in scripting languages such as Python or TCL.
  • Experience using EDA tools including HDL simulators, lint tools, and FPGA tools.
  • Ability to work long hours and weekends to support critical milestones.
  • Willingness to travel for off-site testing.
  • Must be a U.S. citizen, permanent resident, or eligible for export control authorizations.

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