Sr. ASIC Design Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Hawthorne, CA
Salary: $160,000–$225,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $169k

This role $192k

$124k most similar roles pay here $236k

This role pays more than 64% of similar roles. Most pay $135,000–$202,850 — the shaded band above. At the midpoint, this role pays about $192k versus about $169k for comparable roles.

Based on 239 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. ASIC Design Engineer (Starshield)

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As a Senior ASIC Design Engineer at Starshield in Hawthorne, CA, you will join a cutting-edge team focused on national security solutions. Your primary responsibilities include designing and implementing complex RTL (Register Transfer Level) logic for FPGA/ASIC development, ensuring adherence to standards such as AXI and AHB protocols. You will work closely with cross-functional teams to deliver high-performance hardware solutions that address critical business challenges in the aerospace and defense sector. Ideal candidates have at least 5 years of experience in ASIC design and possess strong skills in Verilog or SystemVerilog, alongside a deep understanding of digital logic design principles. This role demands expertise in verification methodologies and scripting languages like Python for automation tasks.

Skills

AXI AHB RTL FPGA ASIC

What you'll do

Design and implement complex RTL for FPGA/ASIC development.
Optimize and debug RTL code to meet performance requirements.
Develop verification plans and testbenches for ASIC designs.
Collaborate on the integration of IP cores into system-level designs.
Ensure compliance with design standards and methodologies.

What we're looking for

5+ years of experience in RTL implementation and FPGA/ASIC development.
Proficiency in AXI, AHB, and other bus protocols.
Strong understanding of ITAR requirements for U.S. Department of State compliance.
Experience with ASIC design and verification methodologies.
Bachelor’s degree or higher in Electrical Engineering, Computer Science, or related field.
Excellent problem-solving skills and ability to work on complex projects.

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