Sr. ASIC Design Verification Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Hawthorne, CA
Salary: $160,000–$225,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $175k

This role $192k

$128k most similar roles pay here $235k

This role pays more than 59% of similar roles. Most pay $138,300–$211,475 — the shaded band above. At the midpoint, this role pays about $192k versus about $175k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. ASIC Design Verification Engineer (Starshield)

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The Sr. ASIC Design Verification Engineer role at Starshield in Hawthorne, CA involves working on advanced national security projects within a specialized engineering team. This senior-level position focuses on developing and maintaining verification methodologies for complex ASIC designs, automating test cases with Python, and ensuring high-quality design validation through rigorous testing protocols. Candidates should possess expertise in digital design verification, experience with UVM/OVM verification frameworks, and proficiency in SystemVerilog or VHDL. The ideal candidate will also have a strong background in scripting languages like Python for automation tasks and a deep understanding of semiconductor technology and verification processes at large-scale enterprise levels.

Skills

Python ASIC Verification CI/CD

What you'll do

Develop and execute verification plans for complex ASIC designs.
Create test benches, simulations, and validation scripts to ensure design integrity.
Identify and debug issues in hardware logic using advanced verification methodologies.
Collaborate on the creation of reusable verification IP (VIP) components.
Automate verification processes using Python scripting for efficiency.

What we're looking for

Extensive experience in ASIC design verification required.
Proficiency in Python for automation and scripting essential.
Strong background in creating testbenches and simulations necessary.
Knowledge of ITAR requirements and compliance mandatory.
Bachelor’s degree in Electrical Engineering, Computer Science or related field.

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