Senior ASIC Design Engineer - Hardware

Nvidia

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $136,000–$218,500 / yr
Posted: 17 days ago

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k

This role $177k

$125k most similar roles pay here $236k

This role pays less than 52% of similar roles. Most pay $162,775–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer - Hardware

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As an ASIC Design Engineer at NVIDIA’s System-On-Chip group, you will play a crucial role in defining and delivering system-level methodologies and RTL for performance measurement across multiple GPU and SOC projects. Your responsibilities include automating flows, designing microarchitecture features, running RTL checks, and collaborating with architects and software engineers to ensure high-quality designs. The ideal candidate has 3+ years of industry experience with strong skills in Perl/Python or similar scripting languages, along with expertise in Verilog, SystemVerilog, and SOC design automation tools such as dc_shell and VCS. A deep understanding of SOC architecture, including cross-clock domain issues and performance analysis, is essential, alongside excellent communication and collaboration abilities to work effectively within the team and across functions.

Skills

Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes Terraform CI/CD Git Unix/Linux

What you'll do

Define and develop system-level methodologies for measuring performance in GPUs and SOCs.
Automate flows and support projects using the performance monitoring system.
Implement RTL features and microarchitecture designs for IP delivery.
Run and debug RTL checks to ensure quality across various design aspects.
Collaborate with architects, designers, and software engineers on tasks.

What we're looking for

3+ years of industry experience in ASIC or SOC design
Strong coding skills in Perl, Python, or other scripting languages
Proficiency in RTL design (Verilog) and verification (SystemVerilog)
Understanding of SOC architecture including CDC and multiple power domains
Experience with design automation tools and methodologies
Hands-on experience in system-level IP development (Clocks/DFT/Resets)
Excellent communication and collaboration skills for cross-functional teams

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