ASIC Design Engineer, Hardware

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $116,000–$189,750 / yr
Posted: 9 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $153k

$103k most similar roles pay here $237k

This role pays less than 82% of similar roles. Most pay $162,000–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Hardware

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As an ASIC Design Engineer - Hardware within the System-On-Chip group, you will focus on improving methodologies and delivering system-level IP to measure performance across multiple projects. Your daily responsibilities include defining, developing, and automating flows to build and support system-level IP while running and debugging RTL checks for cross clock domains, clocks, resets, and latency. You will design and implement microarchitecture and RTL features while collaborating with architects, designers, and software engineers. The role requires proficiency in Verilog for RTL design, SystemVerilog for verification, and scripting languages like Perl or Python. You must possess a strong understanding of SOC architecture, including multiple-power domains and data flow. Technical expertise includes using tools such as dc_shell, VCS, Debussy, and GDB to ensure high design quality for leading GPUs and SOCs.

What does a ASIC Design Engineer earn?

Median $214000 from 51 postings across 9 companies.

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Skills

RTL Verilog SystemVerilog Python Perl SoC CDC Synthesis VCS GDB Debussy dc_shell DFT Microarchitecture Scripting Silicon Debug Physical Design

What you'll do

Develop and deliver system-level RTL to measure performance on GPUs and SoCs.
Create and automate flows and methodologies to build and support system-level IP.
Implement microarchitecture and RTL features for SoC designs.
Run and debug RTL checks including cross clock domains, clocks, resets, and latency.
Apply performance monitoring systems to deliver and support various projects.
Utilize scripting languages like Perl or Python to automate design processes.
Perform silicon debugging and analysis using industry-standard synthesis and simulation tools.

What we're looking for

BS degree in Electrical Engineering, Computer Engineering, or a related field is required.
MS or PhD degrees are considered a plus.
Candidates must have at least 2 years of relevant industry experience.
Strong coding skills in Perl, Python, or other industry-standard scripting languages are required.
Experience in RTL design (Verilog), verification (SystemVerilog), and SoC design/implementation flow is required.
Proficiency in design automation and a good understanding of SoC architecture including CDC, power domains, and performance analysis is required.
Experience with synthesis tools (dc_shell), simulation tools (VCS), and debug tools (Debussy, GDB) is required.
Excellent communication and collaboration skills to work with cross-functional teams are required.

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