ASIC & FPGA Design Engineer Senior

Lockheed Martin

Hybrid

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Work type
Hybrid
Location
Orlando, FL
Posted
3 days ago
Nearby
99+ roles within 25 mi

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About Lockheed Martin

Lockheed Martin is a global aerospace, defense, and security company that designs, develops, and manufactures advanced technology systems, products, and services for government and commercial customers worldwide.

Lockheed Martin currently has 611 open roles on FindRole.

Listed pay typically runs $101,000–$178,135 across 304 roles with salary data.

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TL;DR · ASIC & FPGA Design Engineer Senior

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As a Senior ASIC & FPGA Design Engineer on the Programmable Logic Design team at Lockheed Martin, you will be responsible for architecting and developing critical programmable logic components that power precision engagement aerospace systems. Your day-to-day tasks include defining design specifications, writing clean RTL code in VHDL/Verilog/SystemVerilog, and implementing synthesis strategies to ensure deterministic operation across FPGA families. You’ll also build comprehensive test plans using UVM and Python-based testbenches, lead hardware-in-the-loop testing, and collaborate with cross-functional teams to maintain project timelines and performance standards. Essential skills include proficiency in Xilinx/AMD toolsets like Vivado and Vitis, experience with high-speed interfaces such as AXI and PCIe, and a strong understanding of digital design principles. This role requires a US citizenship and the ability to obtain a DoD Secret clearance.

Skills

VHDL Verilog SystemVerilog Xilinx Vivado AMD Vitis UltraScale design methodology Synopsys VCS AXI Ethernet TCP/IP PCIe Serial protocols High-speed oscilloscopes Spectrum analyzers Signal generators Synopsys EDA tools Simulink HDL Coder C/C++ DSP

What you'll do

  • Define architecture and design specifications for programmable logic components.
  • Develop synthesis strategies to achieve deterministic operation on target FPGA families.
  • Build comprehensive test plans and verification environments using UVM, SystemC, Python.
  • Lead hardware in the loop testing and board level debugging activities.
  • Perform timing analysis and power budgeting studies to optimize FPGA utilization.

What we're looking for

  • Bachelor’s degree in Electrical Engineering or related STEM field; Master’s preferred
  • At least 3 years of professional FPGA design and simulation verification experience
  • Proficiency in VHDL, Verilog, SystemVerilog for HDL programming
  • Experience with Xilinx/AMD toolsets (Vivado, Vitis) and UltraScale design methodology
  • Strong understanding of digital design principles including timing analysis and signal integrity
  • Practical laboratory debug skills using high-speed oscilloscopes and signal generators
  • Familiarity with Synopsys EDA tools for FPGA development

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