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Active Keyword: ASIC Design Remove filter Clear all

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Staff Engineer, ASIC Design Verification

Samsung Semiconductor

San Jose, CA 2 days ago $163,000–$253,000
Actively hiring Posted this week Verified listing Competitive pay
UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD
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Manager, ASIC Design Engineering (Starshield Silicon)

SpaceX

Hawthorne, CA 2 days ago $190,000–$245,000
Actively hiring Posted this week Verified listing Above market
RTL FPGA ASIC AXI AHB VHDL Verilog SystemC Cadence Synopsys Xilinx Altera Mentor Graphics JTAG UVM Linux Git CI/CD Python Matlab
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FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX

Redmond, WA 2 days ago $125,000–$145,000
Actively hiring Posted this week Verified listing Below market
SystemVerilog Verilog Python C C++ Bash DSP AXI AHB APB FPGA ASIC Microprocessors Oscilloscopes Spectrum Analyzers
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ASIC Clocks Design Engineer - New College Grad 2026

Nvidia

Santa Clara, CA 3 days ago $100,000–$166,750
Actively hiring Posted this week Verified listing Below market
Verilog Python RTL Docker CI/CD VLSI Sub-micron silicon issues Noise Cross-talk OCV effects Clocking networks Power Optimization Physical Implementation DFx Timing Closure
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ASIC Design Efficiency Engineer

Nvidia

Santa Clara, CA 4 days ago $116,000–$189,750
Actively hiring Posted this week Verified listing Below market
SystemVerilog Python Perl VLSI Synthesis PerformanceVerification LowPowerDesign PipelineProcessorDesign DeepLearningAcceleratorArchitecture CI/CD
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Senior ASIC Design Engineer – Clocks IP

Nvidia

Santa Clara, CA 16 days ago $136,000–$218,500
Actively hiring Verified listing Competitive pay
Verilog Python RTL Logic Synthesis CI/CD Sub-micron Silicon Issues Clocking Networks Clocks Controller Power Optimization Noise Analysis Cross-talk OCV Effects Scalable Designs Silicon Debug
Hybrid
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Senior ASIC Floorplan Design Engineer

Nvidia

Santa Clara, CA 16 days ago $196,000–$310,500
Actively hiring Verified listing Above market
Verilog SystemVerilog Python Perl C++ CAD VLSI ComputerArchitecture ChipFloorplan PowerClockDistribution Packaging P&R TimingClosure
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Senior ASIC Design Engineer - Hardware

Nvidia

Austin, TX 17 days ago $136,000–$218,500
Actively hiring Verified listing Competitive pay
Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes Terraform CI/CD Git Unix/Linux
Hybrid
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Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 17 days ago $168,000–$264,500
Actively hiring Verified listing Above market
Verilog System-Verilog RTL ASIC Logic Design Computer Architecture Digital Systems Timing Analysis ECO Post Silicon Debug Arbiters Scheduling Synchronization Bus Protocols Interconnect Networks Switches Virtual Channels
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