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ASIC SoC RTL GDS2 FPGA SerDes DSP SPI I2C APB AXI Ethernet DFT Synthesis Timing Closure Low-Power Design Scripting +12 more Show less

ASIC Design SystemVerilog Verilog HDL UVM RTL Design FPGA Static Timing Analysis (STA) Logic Synthesis Lint CDC IP Integration PPA Machine Learning LLM Acceleration NPU TCP/IP Ethernet Altera AMD Xilinx +14 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis +12 more Show less

ASIC Signal Integrity Power Integrity Cadence Sigrity Ansys HFSS Keysight ADS SPICE Cadence APD Ansys EM PAM4 SerDes 2.5D Fanout HBM UCIe IBIS Vector Network Analysis Transmission Line Theory Electromagnetics PCB. Design Mixed-Signal Circuit Design +14 more Show less

RTL Design HDL SystemVerilog Verilog VHDL UVM Digital Design VLSI Design Synthesis Static Timing Analysis STA Computer Architecture SoC SRAM Design Physical Design P&R Timing Closure Python C++ C Perl TCL Linux Testbench Creation Functional Coverage CMOS Transistors Power and Performance Optimization +22 more Show less

Package Design ASIC SerDes HBM DDR5 Signal Integrity Power Integrity DFx Thermal Modeling Automation Project Management Layout Simulations RF Microwave ADC DAC +12 more Show less

ASIC Design RTL Design Logic Synthesis Timing Analysis SoC Integration Python Perl C++ UCIe Digital Design Verification Methodology Boot Controllers Reset Controllers Memory Controllers DMA +10 more Show less

ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP +15 more Show less

ASIC Signal Integrity Power Integrity Cadence Sigrity Ansys HFSS Keysight ADS SPICE Cadence APD Ansys EM PAM4 SerDes Transmission Line Theory Electromagnetics Vector Network Analysis IBIS HBM UCIe CoWoS EMIB PCB. Design +14 more Show less

Verilog RTL ASIC Design SOC Design Lint CDC RDC Synthesis ECO STA Physical Design Python Perl Tcl GenAI System Architecture +11 more Show less

Verilog RTL ASIC Design SOC Design CDC Lint Synthesis ECO Python Perl Tcl STA Physical Design GenAI System Architecture +10 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC +12 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV Effects SOC Verification +6 more Show less

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl VLSI Design Computer Architecture DMA Engines Bus Protocols Interconnect Networks Digital Systems Computer Arithmetic +11 more Show less

System Verilog UVM Python Perl ASIC Gate Level Simulation Veloce Palladium Zebu HAPS P4 PCIe CXL Ethernet RDMA DDR TCP Formal Verification +13 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

System Verilog UVM Constrained Random Verification VCS Incisive Python Perl SVA OOP Coverage Closure Ethernet AI/ML Scripting +8 more Show less

ASIC Design RTL Design Verilog System Verilog Python Perl Logic Synthesis Timing Analysis VLSI Computer Architecture VCS Verdi GDB Functional Coverage Assertion-Based Verification Embedded Processors SoC GPU +13 more Show less

RTL NoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration SoC Front-end Synthesis +10 more Show less

RTL NoC SoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration Scripting Front-end Synthesis +11 more Show less