Senior ASIC Design Engineer – Clocks IP

Nvidia

Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA · Austin, TX
Salary
$136,000–$218,500 / yr
Posted
16 days ago

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Competitive pay

How this pay compares to similar roles

Similar $190k
This role $177k
$125k most similar roles pay here $236k

This role pays less than 51% of similar roles. Most pay $163,825–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer – Clocks IP

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Join our dynamic Clocks team as an ASIC Engineer where you will architect clock domains to meet functional, physical, and testing requirements for GPU and CPU chips. You’ll engage with various teams to design clocks that satisfy architectural constraints while optimizing Power, Performance, and Area (PPA). Collaborate closely with the physical design and timing team to address high-speed clocking concerns and deliver RTL information to verification and DFT teams throughout the ASIC development cycle. Ideal candidates have a BS in Electrical Engineering or equivalent experience, 3+ years of relevant work history, expertise in Verilog RTL design, logic synthesis, and scripting languages like Python. Bonus points for hands-on silicon debug experience and knowledge of sub-micron silicon issues such as noise and cross-talk.

Skills

Verilog Python RTL Logic Synthesis CI/CD Sub-micron Silicon Issues Clocking Networks Clocks Controller Power Optimization Noise Analysis Cross-talk OCV Effects Scalable Designs Silicon Debug

What you'll do

  • Design GPU and CPU clocks to meet architectural, physical, and testing requirements.
  • Evaluate trade-offs between Power, Performance, Area (PPA) for clocking topologies in RTL.
  • Collaborate with physical design teams to develop solutions for high-speed clocking concerns.
  • Deliver clock RTL information to verification, timing, and DFT teams throughout the project.
  • Engage in end-to-end ASIC execution from micro-architectural design through silicon bringup.

What we're looking for

  • 3+ years of relevant ASIC engineering experience
  • BS in Electrical Engineering or equivalent; MS preferred
  • Deep knowledge of logic optimization techniques and PPA trade-offs
  • Proficiency in RTL design (Verilog) and logic synthesis
  • Strong coding skills in Python or other scripting languages
  • Experience with on-chip clocking networks and clocks controller logic

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