ASIC Clocks Design Engineer - New College Grad 2026

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA · Austin, TX
Salary
$100,000–$166,750 / yr
Posted
3 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $181k
This role $133k
$86k most similar roles pay here $233k

This role pays less than 96% of similar roles. Most pay $153,100–$209,750 — the shaded band above. At the midpoint, this role pays about $133k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · ASIC Clocks Design Engineer - New College Grad 2026

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Join our dynamic team as an ASIC Clocks Design Engineer at NVIDIA, where you will play a pivotal role in crafting GPU and CPU clocking solutions. You will architect clock domains to meet functional, physical, and testing requirements while collaborating with various teams including front design, floor-planning, back-end, software, and silicon solution teams. Your responsibilities include improving the PPA of innovative chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization, and Ease of timing closure, as well as developing new clocking topologies in RTL. You will also work closely with physical design and timing teams to address high-speed clocking concerns and deliver critical information to verification and DFT teams throughout the ASIC execution cycle. Ideal candidates have a strong background in electrical engineering, experience with Verilog for RTL design and logic synthesis, proficiency in Python or other scripting languages, and an understanding of sub-micron silicon issues such as noise, cross-talk, and OCV effects.

Skills

Verilog Python RTL Docker CI/CD VLSI Sub-micron silicon issues Noise Cross-talk OCV effects Clocking networks Power Optimization Physical Implementation DFx Timing Closure

What you'll do

  • Design GPU or CPU clocks to meet architectural, design, and physical constraints.
  • Architect clock domains to satisfy functional, physical, and testing requirements.
  • Evaluate trade-offs in PPA for innovative clocking topologies in RTL.
  • Collaborate with physical design team to develop solutions for high-speed clocking.
  • Provide clock RTL information to verification, timing, and DFT teams.
  • Involved in end-to-end ASIC execution from micro-arch to silicon bringup.

What we're looking for

  • Bachelor’s degree or higher in Electrical Engineering (or equivalent experience).
  • Experience in RTL design (Verilog) and logic synthesis.
  • Strong coding skills in Python or other scripting languages.
  • Understanding of PPA trade-offs and logic optimization techniques.
  • Ability to collaborate with multiple teams across the design process.
  • Knowledge of sub-micron silicon issues like noise, cross-talk, and OCV effects.
  • Experience implementing on-chip clocking networks.

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