FPGA/ASIC Design Engineer, Silicon Engineering

SpaceX

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$125,000–$145,000 / yr
Posted
113 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $197k
This role $135k
$112k most similar roles pay here $242k

This role pays less than 92% of similar roles. Most pay $168,125–$226,025 — the shaded band above. At the midpoint, this role pays about $135k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · FPGA/ASIC Design Engineer, Silicon Engineering

Role Posting Log in to save

The FPGA/ASIC Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation FPGAs and ASICs for space and ground infrastructure. This role involves designing complex SoC blocks, performing integration tasks, and optimizing designs for power, performance, and area throughout the full design lifecycle. The engineer will participate in architectural discussions, microarchitecture, and design partitioning while collaborating with software engineers on production code and building tools to analyze orbital data. Key technical requirements include proficiency in Verilog, SystemVerilog, or VHDL for RTL design, along with experience in Python, C/C++, and Bash. Candidates should possess knowledge of AXI/AHB/APB protocols, EDA tools like Vivado or Quartus, and hardware debugging using oscilloscopes. The work focuses on solving connectivity challenges by developing high-performance components for the Starlink network's communication and signal processing systems.

Skills

ASIC FPGA Verilog SystemVerilog VHDL Python C++ Bash EDA Tools VCS Questa Spyglass Xilinx Vivado Altera Quartus II AXI AHB APB DSP

What you'll do

  • Design ASICs and FPGAs for Starlink projects using Verilog and SystemVerilog.
  • Implement complex SoC blocks and perform SoC integration tasks.
  • Optimize hardware designs for power, performance, and area constraints.
  • Manage the full ASIC/FPGA lifecycle from architectural discussion to lab bring-up.
  • Build physical and digital tools to analyze data collected in the lab and on orbit.
  • Design test systems to support FPGA/ASIC validation and integration with communication subsystems.
  • Develop production software in collaboration with software engineering teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog, or VHDL.
  • Experience with ASIC/FPGA system integration and optimization for power, performance, and area.
  • Proficiency in Python, C/C++, and Bash.
  • Experience designing DSP, digital communication system datapath blocks, and modem designs.
  • Experience with EDA tools including HDL simulators, lint tools, and FPGA tools like Vivado or Quartus.
  • Understanding of AXI, AHB, and APB protocols.
  • Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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