FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$125,000–$145,000 / yr
Posted
today

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k
This role $135k
$113k most similar roles pay here $237k

This role pays less than 91% of similar roles. Most pay $161,500–$216,250 — the shaded band above. At the midpoint, this role pays about $135k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · FPGA/ASIC Design Engineer (Silicon Engineering)

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Join the Silicon Engineering team as an FPGA/ASIC Design Engineer, where you will design and optimize complex SoC blocks for Starlink projects using Verilog/SystemVerilog. Your day-to-day responsibilities include participating in the full lifecycle of ASIC/FPGA development from high-level conceptualization to lab bring-up and validation, collaborating with backend teams, and contributing to the creation of tools for data analysis. You will also engage in architectural design for test systems and work closely with software engineers to develop production software. Essential skills include proficiency in SystemVerilog, Python, C/C++, Bash, and experience with AXI/AHB/APB protocols, as well as a strong background in electrical engineering fundamentals and hands-on debugging of complex PCBs.

Skills

SystemVerilog Verilog Python C C++ Bash DSP AXI AHB APB FPGA ASIC Microprocessors Oscilloscopes Spectrum Analyzers

What you'll do

  • Design complex SoC blocks and integrate them using Verilog/SystemVerilog for Starlink projects.
  • Optimize FPGA/ASIC designs for power, performance, and area efficiency.
  • Participate in the full lifecycle of ASIC/FPGA design from concept to validation.
  • Build tools to analyze data collected on orbit and in the lab for continuous improvement.
  • Engage in high-level architectural design for test systems supporting FPGA/ASIC validation.

What we're looking for

  • 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
  • Experience in designing DSP, digital communication system datapath blocks, and/or modem design
  • Proficiency in Python, C/C++, and Bash scripting
  • ASIC/FPGA system integration experience and understanding of AXI/AHB/APB protocols
  • Strong foundation in electrical engineering fundamentals and lab debugging skills

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