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Python SystemVerilog UVM VCS Verdi Jenkins Make CI/CD Perl Docker Kubernetes Terraform AWS GCP Git GitHub Mercurial SVN Prometheus Grafana AI Machine_Learning +17 more Show less

Cadence Virtuoso Dracula Hercules Calibre Primeyield Perl Python SKILL DRC LVS +6 more Show less

Python C++ PyTorch LangChain LangGraph AI/ML EDA VLSI ASIC Deep Learning Agentic Systems Autonomous Optimization CI/CD PostgreSQL MESOS +10 more Show less

NVLink PCI-Express Ethernet UCIE ASIC RTL Verilog System-on-Chip Network-On-Chip High-speed connectivity protocols Chip architects Verification engineers Formal verification engineers SoC integration engineers Data movers Protocol adaptors Arbiters Schedulers +13 more Show less

AWS Azure GCP Python C++ SQL ETL Kubernetes Terraform CI/CD Prometheus PostgreSQL Docker Git AI ML Gen AI Data Modeling Algorithm Design +14 more Show less

C++ Python ICCAD tools Innovus Computational geometry Graph theory Algorithm development Multithreading Distributed computing High performance software design GUI development Machine learning VLSI Physical Design +8 more Show less

Verilog SysVerilog C++ Python Perl TCL AgenticAI ClaudeCode Cursor CoPilot EDA ASIC Design for Testing Scan ATPG JTAG +11 more Show less

Verilog Python RTL Logic Synthesis CI/CD Sub-micron Silicon Issues Clocking Networks Clocks Controller Power Optimization Noise Analysis Cross-talk OCV Effects Scalable Designs Silicon Debug +9 more Show less

Verilog SystemVerilog Python Perl C++ CAD VLSI ComputerArchitecture ChipFloorplan PowerClockDistribution Packaging P&R TimingClosure +8 more Show less

Python Perl RTL EDA tools SOC integration Design automation flows Synthesis Padring Physical design +4 more Show less

Verilog System-Verilog RTL ASIC Logic Design Computer Architecture Digital Systems Timing Analysis ECO Post Silicon Debug Arbiters Scheduling Synchronization Bus Protocols Interconnect Networks Switches Virtual Channels +12 more Show less

Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence +9 more Show less

Perl TCL Make Python RTL Logic Synthesis Equivalence Checking Clock Domain Crossing Checks MTBF Analysis Static Timing Analysis Timing Constraints Management EDA Tools DFT Timing Closure AI Utilization +9 more Show less

Perl Python Tcl Make SPICE Liberty models Deep Learning GPU Parallel Computing CI/CD +5 more Show less

Cadence_Virtuoso Calibre Python TCL Perl SKILL C++ AI Automation DOE DRC LVS Silicon_Photonics CMOS Custom_Layout SDL ICV Dracula Primeyield +14 more Show less

Python PyTorch TensorFlow LangGraph LangChain Ray NetworkX PrimeTime Nanotime Tempus CI/CD EDA VLSI ASIC STA Knowledge Graphs Process Models Multi-Agent Systems Graph Neural Networks Large Language Models +15 more Show less

PCIe CXL AXI CHI Verilog SystemVerilog RTL design performance analysis power optimization Data link layer Physical layer Memory (DDR, LPDDR) SerDes Python CI/CD +10 more Show less

Spice Perl Tcl Make RTL Logic Synthesis Verification Place and Route Design-for-test(DFT) Analog Circuit Design Mixed-Signal Analog Block Design Digital Circuit Design Security Attacks Detection Circuits EM/IR Analysis Static Timing Analysis Noise Analysis Loop Stability Analysis Monte-Carlo Analysis +13 more Show less

Verilog SystemVerilog Vivado Quartus Diamond Xilinx Altera Lattice I2C SPI JTAG PCIE USB Ethernet Encryption Python Perl FPGA CPLD ASIC RTL DFT SI Schematics Layout CI/CD +21 more Show less

Verilog System-Verilog Python Perl Tcl Makefiles CDC checks Formal equivalence RTL design Synthesis Timing analysis DFT ATE test development Post-si bringup Debugging Behavioral real number modeling Mixed signal design Custom designed IPs Agentic AI flows +14 more Show less