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Mask Design Layout Design DRC LVS Python Perl Skill Calibre ICV Thunder Submicron CMOS Signal Integrity Auto-routing Netlists Silicon Interposers +10 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis +12 more Show less

Physical Design EDA Tools PPA TCL Python C++ Perl Cadence Innovus Genus Tempus Quantus Joules STA UPF FSDB SAIF PyTorch NumPy SciPy scikit-learn ML AI Synthesis DFT +20 more Show less

ASIC Design RTL Design Logic Synthesis Timing Analysis SoC Integration Python Perl C++ UCIe Digital Design Verification Methodology Boot Controllers Reset Controllers Memory Controllers DMA +10 more Show less

Circuit Design RTL Layout Spice EM/IR Analysis Static Timing Analysis PnR Logic Synthesis Python Perl Tcl Make Power Gating DRC LVS Post-Silicon Characterization Hardware Security AI/ML +13 more Show less

CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding +9 more Show less

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl VLSI Design Computer Architecture DMA Engines Bus Protocols Interconnect Networks Digital Systems Computer Arithmetic +11 more Show less

SOC Design RTL Design ASIC Design Physical Design DFT EDA Tools Python Perl Synthesis Padring SOC Integration Design Automation Front-end Chip Implementation +8 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

GPU CPU SoC Tegra System Validation Oscilloscope Multimeter Logic Analyzer Electrical Engineering +4 more Show less

ASIC Design RTL Design Verilog System Verilog Python Perl Logic Synthesis Timing Analysis VLSI Computer Architecture VCS Verdi GDB Functional Coverage Assertion-Based Verification Embedded Processors SoC GPU +13 more Show less

Physical Design Python C++ Perl DFT Place and Route Timing Closure Power/Clock/Reset Distribution Agentic AI Chiplet Packaging Algorithm Development +7 more Show less

ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces +10 more Show less

Mixed Signal Design CMOS Cadence Verilog Matlab PLL Transceivers CDR Data Converters High-Speed IO Timing Analysis Signal Integrity Power Integrity Silicon Characterization Lab Instrumentation Nanotime +11 more Show less

VLSI Physical Design P&R Timing Closure Static Timing Analysis IR Drop Analysis Physical Verification RC Extraction Python Perl Tcl Make Synopsys (ICC2 Cadence (Innovus Mentor Graphics ASIC Power Distribution Clock Distribution +12 more Show less

Python Machine Learning Deep Learning PyTorch TensorFlow LLM VLSI Design CI/CD Version Control Software Development AI Agents +6 more Show less

ASIC Design SoC Design Verilog SystemVerilog C++ Python Perl Tcl Synopsys Fusion Compiler Data Structures Algorithms Build Infrastructure RTL Agentic AI Claude Code Cursor +11 more Show less

Mask Layout Design Cadence Virtuoso FinFET CMOS DRC LVS ICV Calibre Python Perl SKILL Mixed-Signal SerDes RF Layout VLSI Floor Planning Tape-out +13 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV SOC Verification +6 more Show less

ASIC Design RTL Verilog Micro-architecture VLSI Logic Synthesis Timing Analysis DFT Computer Architecture PCI-Express CXL Python Perl C/C++ CMOS Post-silicon Validation Floor-planning ECO Bus Protocols Interconnect Networks +15 more Show less