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Verilog SystemVerilog C++ Python Perl Tcl SoC Design ASIC Design RTL Data Structures Algorithms Synopsys Fusion Compiler AI Coding Tools Claude Code Cursor +10 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Power Optimization Fuse Controller Verification Synthesis +10 more Show less

PCB Design Oscilloscopes Multimeters Logic Analyzers Linux Windows GPU Tegra System Design +4 more Show less

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting +8 more Show less

ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers +10 more Show less

SOC Integration RTL Design Python Perl EDA Tools Synthesis Padring Physical Design ASIC Design Design Automation Scripting DFT CAD +8 more Show less

Circuit Design Mixed-Signal Analog Digital Spice Static Timing Analysis EM/IR Analysis RTL Logic Synthesis Place and Route DFT Perl Tcl Make Automated Tools Transistor-level Analysis +11 more Show less

Python Data Pipelines LLM System Software Silicon Bring-up Productization Engineering DFT DFP ATE SLT BLT L10+ +7 more Show less

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis VLSI Computer Architecture C++ Python Perl Bus Protocols Interconnect Networks DMA Engines Digital Systems +10 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

Python C++ PyTorch LangChain LangGraph Deep Learning Machine Learning EDA VLSI ASIC Circuit Design SPICE Data Science Agentic Workflows Design Automation QOR Silicon Analysis Automation Algorithms +13 more Show less

Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture +7 more Show less

Verilog System-Verilog ASIC Design RTL Logic Synthesis Timing Analysis Computer Architecture GPU Memory Systems Interconnect Networks ECO AI Workflows Autonomous Agents +8 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture +9 more Show less

Power Modeling Circuit Simulation Analog and Digital Circuits Power Delivery Networks (PDN) Ansys Sigrity Matlab Simulink Simplis Spice verilogAMS Cadence Virtuoso Allegro HSpice Spectre Primesim Python Tcl Perl Skill +15 more Show less

Standard Cell ROM SPICE DRC LVS Perl Tcl Make EM/IR SRAM flip flops Level Shifters Circuit Design Layout Automation +10 more Show less

ASIC Design Verilog System-Verilog RTL VLSI Digital Design Synthesis Timing Analysis CDC Formal Equivalence Python Perl Tcl Make files DFT mixed signal Post-Si Bringup Agentic AI +13 more Show less

System Verilog UVM SVA Verilog VCS Questa Perl Tcl Make files Gate Level Simulation Formal Equivalence LLMs Agentic AI Frameworks Mixed Signal Design Functional Coverage Co-simulation +11 more Show less

C++ VLSI Physical Design EDA Tools Machine Learning Graph Neural Networks Python Tcl Perl multithreading Distributed Computing ICC2 Innovus PrimeTime Tempus StarRC +10 more Show less

Verilog System Verilog RTL Design PCIe CXL AXI CHI SerDes DDR LPDDR Link Layer Physical Layer Power Optimization Performance Analysis Chiplets NVLINK-C2C +11 more Show less