Senior Software R&D Engineer, Digital Logic Synthesis
Nvidia
At a glance
AI generatedAs a Senior Logic Design Engineer in the DGX FPGA Logic Team, you will lead the development of FPGA/CPLD designs for advanced Data Center products focused on artificial intelligence. Your responsibilities include defining micro-architectural requirements, writing high-quality RTL code, and ensuring synthesis and timing closure while collaborating with verification teams to validate your design. You will also support system bring-up and validation at various global sites, requiring up to 20% travel. Essential skills include Verilog/SystemVerilog expertise, experience with FPGA EDA tools like Vivado or Quartus, and knowledge of industry-standard protocols such as I2C, SPI, and PCIe. Familiarity with embedded C, Python, and Perl is beneficial, along with a strong background in ASIC/FPGA/CPLD development flows. This role demands excellent communication skills and the ability to mentor junior engineers while working in a dynamic, distributed team environment.
Skills
What you'll do
What we're looking for
Market check
This $136,000–$218,500 range sits above 68% of similar postings on FindRole.
Peer median band
$125,413–$215,500
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$142,400–$201,437
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has 801 open roles on FindRole.
Listed pay typically runs $184,000–$287,500 across 797 roles with salary data.
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